Abstract
We present in this paper the design and implementation of a multilayer 6-bit resistor ladder network capable of operating up to 50 GHz for use in superconductor flash analog to digital converters (ADCs). Implementation of such a resistor network requires the design and optimization of various resistors (25 Ohm, 37.5 Ohm, and 50 Ohm). It is important to minimize the parasitic elements (inductance and capacitance) associated with resistor layout in-order to maintain the performance of the resistor ladder network up to 50 GHz. The paper proposes the use of floating niobium layers around the resistor layer to minimize parasitic effects. The fabricated 6-bit resistor network has a size of 3.2 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$ \times $</tex-math></inline-formula> 3.2 mm and is tested in a Lake Shore Cryogenic probe station. The measured results for the individual resistors and the overall integrated network are in agreement with the EM simulation results.
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