A 4 GS/s, 1.8 V multiplexer encoder based flash ADC using TIQ technique

Abstract

Analog-to-Digital converters (ADC) are useful components in signal processing and communication systems. In the digital signal processing (DSP) low power and low voltage are of prime concern and it is challenging to design high speed mixed signal circuits. This paper describes the ultra high speed ADC design using a 2×1 multiplexer based encoder that is highly suitable and accurate. Speed is an important parameter that is enhanced by using 2×1 multiplexer encoding network. In this paper a 4-bit, 1.8 V, high speed, low power, and low voltage CMOS flash ADC for SoC applications has been proposed. The 4-bit Flash type ADC has been designed with a step size of 0.038125 V. The proposed ADC architecture utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded Complementary Metal oxide semiconductor (CMOS) inverters as a comparator. The high speed and low power TIQ flash ADC architecture is designed and simulated using level 3 spice models. The ADC is designed with a 4 bit resolution and is simulated in 0.12 μm standard CMOS that offers a high data conversion rate of 4 Giga Samples/sec. Differential (DNL) errors measured are between -0.174 LSB to +0.256LSB. The ADC consumes 6.2031 mW from a 1.8 V supply with dynamic range of 600 mV.