Design and analysis of high speed and low power 6-bit flash ADC

Abstract

This paper proposes a high speed and low power 6 bit flash Analog to Digital Converter (ADC) architecture. It comprises of a simple two-transistor based Threshold Inverter Quantizer (TIQ) comparator, modified sample and hold circuit; and ROM encoder. The area and power consumed by the overall ADC architecture is reduced since the comparator transistor count is minimized to two. Existing non-clocked comparators are redesigned and analyzed for appropriate comparison with the proposed comparator. The 6 bit flash ADC consumes a total power of 8.8 mW at an operating speed of 2 GHZ while a single two-transistor based TIQ comparator consumes 0.8679 nW power and has a propagation delay of 46.31 ps for a supply voltage of 1.8 V. The design is implemented in Cadence Virtuoso analog design environment using 180 nm CMOS technology.