Flash Analog-to-digital Converter Research Articles

Высокоточный двухступенчатый АЦП с изменяемым диапазоном сравнения с использованием компаратора на основе защелки

Due to the technology development and decreasing supply voltages, undesirable effects on sensitive analog signals like noise, kickback are becoming more expressed. Mentioned issues are present in analog to digital converters (ADC) and design of high accuracy ADCs is becoming more complex. In this work, a circuit was proposed based on a latch comparator and comparison range shifter, which increased the accuracy of a two-step flash ADCs by excluding the chance of incorrect coarse conversion, when the input analog voltage is close to separating points of the comparison range of first stage of the ADC. The proposed circuit was constructed using an 16nm FinFET process, the simulations were done with HSpice simulator. The idea was to increase the accuracy of an already designed two-step flash ADC by adding the proposed circuit, which was done by shifting the comparison range during the coarse conversion, for the difference of input voltage and separating points not to be smaller than the offset of comparators used in ADC. It was established that the use of the proposed circuit increased the comparison time, as the sampled input analog voltage firstly should be compared with comparison range separating points, but on the other hand the ADC became more sensitive to its input change (up to 4mV offset) and was performing stable, excluding the chance of wrong coarse conversion. It has been shown that proposed architecture allows avoiding the use of low offset and high accuracy complex comparators in two-step flash ADCs, which greatly reduces the layout area.

IMPLEMENTATION OF A REDUCED COMPLEXITY HIGH PERFORMANCE DATA ACQUISITION CHIP USING 0.18 MICRON TECHNOLOGY

Data acquisition (DAQ) in the general sense is the process of collecting information from the real world. For engineers and scientists, this data is mostly numerical and is usually collected, stored and analysed using computers. However, most of the input signals cannot be read directly by digital computers. Because they are generally analog signals distinguished by continuous values, while computers can only recognise digital signals containing only the on/off levels. DAQ systems are therefore inevitably necessary, as they include the translation requirements from analog signals to digital data. For this reason, they have become significant in wide range of applications in modern science and technology [1]. The paper precents the disign of a 12-bit high-speed low-power Data Acquisition (DAQ) Chip. In this paper, the disigns of the building block components are aimed at high-accuracy along with high-speed and low power dissipation. A modifided flash Analog-to-Digital converter (ADC) was used instead of the traditional flash proposed DAQ chip operates at 1 GHz master clock frequency and achieves a sampling speed of 125 MS/s. It dissipates only 64.9 mW of power as compared to 97.2 mW when traditional flash ADC was used.

An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS

An 8-bit 1-GS/s asynchronous loop-unrolled (LU) successive approximation register (SAR)-Flash hybrid analog-to-digital converter (ADC) with complementary dynamic amplifiers (CDAs) is presented. The proposed ADC is a combination of an asynchronous LU-SAR ADC and a reference-embedding 8 × interpolating flash (I-Flash) ADC to enhance the conversion speed. Operating the CDAs in a dual-edge manner makes it possible to achieve an 8-bit resolution with only four CDAs and one capacitive digital-to-analog converter (C-DAC), which improves the power and area efficiency as well as the input bandwidth. A prototype ADC implemented in a 28-nm CMOS process occupies a 0.002 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset calibration is 0.59 and 0.82 LSB, respectively. With a 0.499-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) are 45.5 and 59.4 dB, respectively. The measured effective resolution bandwidth (ERBW) is above 3 GHz. The power consumption at 1-GS/s conversion is 2.55 mW with a supply voltage of 1.1 V, leading to a figure of merit (FoM) of 16.6 fJ/conversion-step.

CMOS Schmitt – Inverter-Based Internal Reference Comparator Array for High Temperature Flash ADC

ABSTRACT Localized data conversions for sensors placed under harsh environmental conditions often require Analog to Digital Converters (ADC) capable of working under wide operating temperature range. Even though the fastest analog to digital converter, flash ADC is omitted from the high temperature regime due to the requirements of reference voltage source, reference voltage divider and a comparator array capable of providing stable operation under wide operating temperatures. A CMOS Schmitt inverter-based internal reference comparator array for flash ADC which is efficient in terms of area and power consumption, capable of working under wide temperature range is presented in this paper. The proposed idea replaces the reference voltage source, resistive reference voltage divider and differential comparator array of a conventional flash ADC by an array of suitably sized Schmitt inverters. The circuit was simulated for static and dynamic characteristics with gpdk 180 nm library using cadence virtuoso simulation suite. The voltage transfer characteristic curve (VTC) of the proposed comparator array was found invariable when a temperature sweep in the range of −40 to 170 degree Celsius was performed. Each of the comparator in the proposed array consumes a silicon area of 40.68 and the average dynamic power consumption per cycle is estimated as 103.1 uW.

A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8× Time-Domain Latch Interpolation

A selectively activated 8× time-domain (T-domain) latch interpolation is proposed for low-power high-speed flash analog-to-digital converters (ADCs). Flash ADCs with T-domain latch interpolation perform voltage-to-time (V-to-T) and time-todigital (T-to-D) conversions along with conventional voltage-to-digital (V-to-D) conversion. This reduces the number of dynamic comparators (CMPs) of the V-to-D conversion for low power consumption. A conventional 4× T-domain latch interpolation that obtains 2 bits in T-to-D conversion reduces the number of dynamic CMPs to 17 from the conventional 63 in a 6-bit flash ADC. To further reduce the number of dynamic CMPs, the nonlinearity of the V-to-T conversion is resolved in this work. A large input is used to define a wide linear range in the V-to-T conversion, and only the linear range is used for an 8× interpolation. This enables a 3-bit T-to-D conversion, and thus, the number of dynamic CMPs is reduced to ten in a 6-bit flash ADC. The large input also enables high-speed operation by mitigating the RC time constant requirement of dynamic CMPs. For low-power T-to-D conversion, only two of eight converters in the T-to-D conversion are selectively activated for a conversion cycle. The fabricated 6-bit ADC chip in 1-V 65-nm CMOS achieves a 6-GS/s sampling frequency, a 15.1-mW power consumption, a 31.18-dB SNDR, and an 85-fJ/conversion step figure of merit.

A novel flash‐like all‐metal‐oxide semiconductor analog‐to‐digital converter suitable for system on chips systems

SummaryThe analog‐to‐digital converters (ADCs) play a very important role in electronic products, radar, communication systems and signal processing, to name such a few. In this paper, a novel all‐metal‐oxide semiconductor (MOS) flash‐like analog‐to‐digital converter (FLADC) that consists of five stages is proposed. The design was performed using only MOS transistors, and the proposed ADC works in a way similar to the conventional flash ADC. According to the proposed ADC, there is no need for the comparators used in the conventional flash ADCs, thus resulting in a reduction in both the transistor count and the power consumption. The sound operation and the superiority of the proposed ADC compared to previous works is verified by simulation using the 0.13‐μm complementary MOS (CMOS) technology with a power‐supply voltage, VDD, of 1.2 V. The simulation has been conducted on a 5‐bit FLADC that is built by 276 MOS transistors only which is approximately 32% of the transistor count of the corresponding conventional flash ADC and has no resistors. According to the simulation results, the proposed 5‐bit FLADC consumes 3.23 mW at sampling rate of 0.5 GS/s.

Neural-Network Based Self-Initializing Algorithm for Multi-Parameter Optimization of High-Speed ADCs

This brief proposes a new automatic model parameter selection approach for determining the optimal configuration of high-speed analog-to-digital converters (ADCs) using a combination of particle swarm optimization (PSO) and stochastic gradient descent (SGD) algorithm. The proposed hybrid method first initializes the PSO algorithm to search for optimal neural-network configuration via the particles moving in finite search space with coarse quantization. Using the PSO estimates, the SGD algorithm then finds the global optimum solution. The global search ability of the PSO algorithm and the local search ability of the SGD are thus exploited to determine an optimal solution that is close to the global optimum with reduced latency. Several experiments were constructed to optimize the non-linearities in Nyquist flash and pipeline ADC datasets to show that the neural networks trained by the PSO-SGD algorithm outperform the random search-based performance optimization. Comparative resource analysis of the proposed algorithm is also conducted against the state-of-the-art that highlights improved latencies and performance with similar area and implementation complexity.

A Reconfigurable 0.1–10 MHz DT Passive Dynamic Zoom ADC for Cellular Receivers

This paper presents a multi-mode, dynamically zooming analog to digital converter (ADC). The architecture is based on a 5b interpolating flash ADC as the zooming unit and a passive discrete-time ΔΣ modulator as the fine conversion unit. The proposed ADC provides a dynamic zooming technique, employing an interpolating zooming front-end. The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it suitable for cellular applications including 4G radio systems. By reconfiguring the OSR, bias current, and component parameters, optimal power consumption can be achieved for every mode. The ADC is implemented in 0.13 μm CMOS technology and it achieves an SNDR of 83/75.7/73.2/67 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/4.7/8.1/10.3mW power consumption from a 1.2 V supply.

A Low Cost 4 bit 16 Giga-sample-per-second Analog-to-digital Converter for Radio Astronomy

In this study, a 4 bit, 16 giga samples per second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was designed, manufactured, and characterized for digitizing signals from radio telescopes. For this purpose, an Adsantec ANST7123-KMA flash ADC chip was used. Because this design of chip is not followed the serial ADC JESD204 standard completely, we used a novel channel bonding scheme developed in our previous project for the high-speed serial data input alignment. The PCBA was equipped with a field-programmable gate array (FPGA) mezzanine card (FMC) connector. FMC allowed us to use the FPGA evaluation board by Xilinx as the testing platform. The PCBA enables data acquisition with a wide bandwidth and simplifies the intermediate frequency section. In the current version, the PCBA and the chip exhibit an analog bandwidth of 16 GHz, which facilitates a second Nyquist sampling. The following minimum to maximum performance parameters were obtained from the first and second Nyquist zones: a spurious-free dynamic range of 18–33 dB and an effective number of bits of 2.1–3.7 bits. The board will be ported to the Collaboration for Astronomy Signal Processing and Electronics Research environment, which is open for use by non-profit scientific teams, including the Event Horizon Telescope.

Photonic serial implementation of a flash analog-to-digital converter.

A photonic analog-to-digital converter (ADC) scheme based on multi-wavelength sampling and balanced detection is proposed and experimentally demonstrated. In the approach, a power-weighted multi-wavelength pulsed source is employed to implement sampling, a dispersion element is used to realize temporal walk-off of multi-wavelength pulses, and a thresholding module is applied to implement serial thresholding. The principles of quantization and encoding are similar to that of an electronic flash ADC, but the serial implementation in the given approach avoids the use of large numbers of comparators. A proof-of-concept experiment with three wavelengths is successfully demonstrated. We also discuss the feasibility of the approach and the design of non-uniform quantization by properly setting the power ratio of the multi-wavelength pulses.

Design of low power fault tolerant flash ADC for instrumentation applications

Technological growth has remarkably put their efforts in making the electronic world a powerful one. Analog to digital converter (ADC) is said to be ancestor in the field of transforming analog information into digital form. It is a necessary component in RF and Mixed signal designs. This paper suggests both neither compact NOR based CMOS Linear Tuneable Transconductance Element (NOR-LTE) Comparator and Dynamic Priority Encoder (DPE). The NOR-LTE comparator reduces the power utilization and offset error, which improves the Power Supply Rejection Ratio (PSRR) of an overall circuit design. Dynamic Priority Encoder curtails the transistor count prescribed for Flash ADC. The proposed Fault Tolerant Flash ADC (FT-FADC) framework is implemented using Tanner EDA with 0.25 ​ ​μm CMOS technology. The above suggested FT- FADC achieves 3.44-bit ENOB at 1.5 ​V supply for 500 ​MHz Resolution Bandwidth (RSB). Due to high sampling rate 1.3 ​GS/s it upgrades the throughput rate by 60% and reduces the utilization of power by 47%.

A 5-bit 500MS/s flash ADC with temperature-compensated inverter-based comparators

In this paper, a 5-bit 500MS/s flash analog-to-digital converter (ADC) with temperature-compensated inverter-based comparators is proposed. In the proposed ADC, a complementary-average system structure is adopted. Based on this structure, inverter-based comparators are used to reduce the power consumption. However, conventional inverter-based comparators suffer from switching threshold variation when the temperature changes, which degrades the SNDR performance of the whole ADC. To tackle this problem, a temperature-compensated inverter-based comparator is proposed. Furthermore, an encoder with majority-3 bubble error correction is used in the proposed ADC to reduce bubble errors. To verify the proposed design, a prototype ADC is implemented in a 0.18 µm process. Measurements at room temperature show that the SNDR and SFDR of the proposed prototype are 29.6 dB and 34.92 dB, with a resulting ENOB of 4.62 bits. It achieves an DNL and INL of +0.33 LSB /−0.54 LSB and +0.27 LSB/−0.33 LSB, respectively, and consumes 6 mW from a 1.8-V supply. At 0 °C and 60 °C, the ADC maintains a close performance.

On‐chip tunable Memristor‐based flash‐ADC converter for artificial intelligence applications

This study presents a novel hybrid memristor (MR)-complementary metal–oxide–semiconductor-based flash analogue-to-digital converter (ADC). The speed and efficiency of the ADC are important aspects that can significantly affect the overall system performance. The flash ADC is considered the fastest type of ADCs; however, its performance is affected by the resistor mismatch. The proposed flash ADC is the first to use tunable MR to replace conventional resistor to generate accurate reference voltages. This is achieved by utilising the highly analogue behaviour observed in multi-state MR devices fabricated and tested by the authors' group. The electrical parameters of the devices have been extracted by device characterisation, then the voltage-threshold adaptive model (VTEAM) has been used to develop a correlated mathematical and Simulation Program with Integrated Circuit Emphasis (SPICE) device model. The proposed MR-based flash-ADC design solves the issue of resistor mismatch that results in encoding errors by the ability to tune the MR resistance value post-processing. Moreover, being a nanoscale component, the usage of MR significantly improves the area efficiency of the target ADC. Furthermore, the proposed design has improved the ADC transfer function characteristic and has lower differential non-linearity and integral non-linearity errors compared with the conventional design.

A Suggestive Low Power TIQ Comparator Architecture using Adiabatic Logic for Implementation of 3-bit Flash type ADC.

Power consumption is prime concern for the designers in modern day scenario. For the devices that are power-driven by tiny rechargeable or non-rechargeable batteries over the entire life period, such as medical transplant devices or portable medical instruments, necessitates lowest possible power consumption. In these devices Analog-to-Digital Converter (ADC) isdynamic component to provide connectionamongstAnalog and Digital system. The paper is aimed to report the design contests and tactics for low power ADCs which are used in biomedical graft devices and instruments. A comparator module of ADCs used in designing of such devices requires more power than other blocks in the device, a low power comparator is suggested for Threshold-Inverter-Quantizer (TIQ)usingDiode-Free-Adiabatic-Logic (DFAL) to implement Flash type ADCs. The projected 3-bit Flash ADC is simulated using Cadence ® Virtuoso IC616 with TSMC 65nm technology. The ADC was simulated atpeak to peak voltage of 1.2V andcapacitive load of 1fF,results in consumption of5.53 μW of average power, which is 66.03 % lesser relative toconservative CMOS-TIQ based comparator. Observed static parameters are: DNL is equal to-0.62 / + 0.57 LSB and INL is equal to- 0.44/ +0.41 LSB.Dynamic parameters observed results are as: THD = -25.25dB, SNR=19.45 dB, SNDR=18.39 dB, ENOB=2.76 bits, SFDR = 23.4 dB.

Design of Efficient Low Power Flash ADC Using TIQ in 45 nm Technology

Objective: To design and implement flash ADC for high speed operation thereby to minimise the power consumption and improve the performance efficiency. Methods: At present, there exists a variety of Analog-to-Digital Converter (ADC) with different architecture, sampling rates, resolutions, temperature ranges, and power consumption. The existing ADCs used in various multiple applications which include mobile communication hardware to measuring instruments. Therefore, their significant performance and working of ADCs are determined by its architecture, the commonly existing ADC design is not suitable for all applications. In order to meet the high speed operation scenario, a Flash type ADC model is proposed. Findings: Resistor ladder would be commonly used in all type of ADC circuits, but downside it consume maximum area and power. In all existing methods, the average power consumption of Flash ADC is found to be higher when compared with our methodology. This can be overcome by using threshold inverting quantization (TIQ) comparator for low power operation. Improvements: An efficient thermometer to the binary code converter is targeted for 45 nm CMOS technology that has been proposed and implemented Flash CMOS ADC Design using the CADENCE VIRTUOSO Tool. The optimal power analysis has been carried out to prove the design absolutely a low power model.Keywords: Flash ADC, Low Power, CMOS Technology, TIQ Comparator, CADENCE VIRTUOSO

Design and Simulation of 4-Bit Flash Analog to Digital Converter (ADC) for High Speed Applications

Objective: To design 4-bit flash Analog to Digital Converter (ADC) for high speed applications. The objectives of the project are to design sample and hold circuit, high efficient DAC circuit, to design a high speed, low power and minimum delay CMOS comparator and thermometer to binary code convertor logic. Methodology: The main block of flash ADC is designing of comparator. For high speed applications Flash ADC requires comparator having high sensitivity and low power dissipation. In this we have used CMOS comparator with cascaded stages, each stage will help in increasing gain and sensitivity and reducing the all types of noises. First stage is the pre-amplifier stage whose output is given to the input of decision stage. Decision stage is followed by post-amplifier stage. Findings: In most papers for designing flash ADC they used dynamic comparator, these dynamic comparators are more difficult to design and will give more power dissipation. In our design we used CMOS comparator with cascaded stages, this type of comparator provides less power dissipation, less delay and high sensitivity by reducing the noise like kickback noise, offset voltages etc. The design is simulated in 180 nm Technology with Cadence Virtuoso Tool and LT spice. Designed comparator has Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) error considered for design within +/- 0.5LSB. For N-bit flash ADC we have 2N-1 comparators, whose outputs will generate patterns of 0’s and 1’s in form of thermometer code; in order to convert it into binary format we have used mux encoder. This mux encoder logic reduces area and very easy to design compared to other methods. Applications/ Improvements: Flash ADC’s are used in various applications ranging from radar receivers, digital sampling, and LAN interface. The proposed design achieved a power dissipation of 0.121 mW with delay of 19.4 ns. The comparator block is designed and simulated. The sensitivity of the comparator is 0.003V. Keywords: CMOS Comparator, DNL and Binary Code Converter, Flash Analog to Digital Converter (ADC), Integral NonLinearity (INL)

A Low-Power Low-Distortion 20-GS/s Flash Analog-to-Digital Converter for Coherent Optical Receiver in 0.13-μm SiGe BiCMOS

High-speed, low-power analog-to-digital converter (ADC) is a critical element for 5-GBd, 20-Gb/s digital signal processing (DSP)-based coherent optical communication receiver. To satisfy high data transmission rate requirement of optical receiver, a single-core and open-loop flash ADC with a new proposed multiplexer-based encoder is presented in this paper. Compared with conventional encoder topology, the new proposed topology achieves the fastest encoding speed and lowest power consumption. The optimized distortion is achieved by utilizing a leakage current compensation technique and a local negative feedback method in switched-buffer track-and-hold amplifier (THA). Strict synchronization is obtained for clock signals by careful designing of layout in tree-based clock networks. Furthermore, a master–slave comparator incorporated with a preamplifier reduces signal-dependent kickback noise as well as offset voltage. By using master–slave comparators and proposed encoders, the sampling rate is up to 21.12[Formula: see text]GS/s. The 4-bit, 20-GS/s flash ADC is realized in 0.13-[Formula: see text]m SiGe BiCMOS technology and it only occupies 1.05[Formula: see text]mm[Formula: see text][Formula: see text][Formula: see text]1.46[Formula: see text]mm chip area. With a power consumption of 1.831[Formula: see text]W from 4-V supply, the ADC achieves an effective number of bits (ENOB) of 2.5 at 15[Formula: see text]GS/s.

A Low Power Flash ADC using Single-Electron Transistor

This paper proposes an analog-digital converter (ADC) using Single-electron transistor (SET).Single Electron Transistor is Nanodevice having a small quantum dot or island instead of the channel that works on the principle of Coulomb blockadewhich allows one electron tunnelingat a time from source to drain terminal. SET operates at low voltage and consumes lesspower. The proposed Flash ADC consists of SET based priority encoder and comparator circuits. The proposed design offers large input/output voltage swing, ultra-low power, compact circuit block for ADC compared to SET/CMOS hybrid amplifier-based ADC. In this paper, we have designed a 4-bit and 8bitFlash ADC using SET operating at room temperature and the performance estimationwas performed by using the CADENCE VIRTUOSO simulator.

TIQ Flash ADC Design using a Low Power Multiplier Based Encoder

Threshold Inverter Quantization (TIQ) for applications of system-on-chip (SoC) depending on CMOS flash analog-to-digital converter (ADC). The TIQ technique which uses two cascaded CMOS inverters as a voltage comparator. However, this TIQ method must be created to meet the latest SoC trends, which force ADCs to be integrated with another electronic circuit on the chip and focus on low-power and low-voltage applications. TIQ comparator reduced the impact of variations in the process, temperature, and power supply voltage. Therefore, we obtained a higher TIQ flash ADC speed and resolution. TIQ flash ADC reduced / managed power dissipation. We obtain large power savings by managing the power dissipation in the comparator. Furthermore, the new comparator has a huge benefit in power dissipation and noise rejection comparative to the TIQ comparator [1]. The findings indicate that the TIQ flash ADC based on Modied mux attain heavy-speed transformation and has a tiny size, low-power dissipation and operation of lowvoltage compared to another flash ADCs.

Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme

The sampling rate plays a key role in wireless applications at very high-frequency range. Flash analog-to-digital converter (ADC) betters the slow converter counterparts in this regard but bulky at inevitable high resolutions. A state-of-the-art Divide and Collate (DnC) algorithm is proposed to design the flash ADC at subranging levels. The offset voltage is kept at a minimum through the comparators used for coarse and fine conversion separately. The kick-back noise is also reduced by using sample and hold switches at the input. The 10-bit ADC architecture is designed with 45-nm CMOS technology and analyzed in the SPECTRE environment. A trivial variation in the transconductance with temperature is observed and consequently the offset drift with temperature is found to be 0.015 mV/'C. The design improves the INL by 0.42 LSB and DNL by 0.3 LSB. Signal-to-noise-and-distortion (SNDR) ratio and spurious-free dynamic range (SFDR) are 51.8 dB and 62 dB respectively at a frequency range near the Nyquist rate with a supply voltage of 1 V and input frequency of 500 MHz. Subranging scheme minimizes the comparator requirements which is reflected in the 44% reduction in the power dissipation.