A 5-bit 500MS/s flash ADC with temperature-compensated inverter-based comparators

Abstract

In this paper, a 5-bit 500MS/s flash analog-to-digital converter (ADC) with temperature-compensated inverter-based comparators is proposed. In the proposed ADC, a complementary-average system structure is adopted. Based on this structure, inverter-based comparators are used to reduce the power consumption. However, conventional inverter-based comparators suffer from switching threshold variation when the temperature changes, which degrades the SNDR performance of the whole ADC. To tackle this problem, a temperature-compensated inverter-based comparator is proposed. Furthermore, an encoder with majority-3 bubble error correction is used in the proposed ADC to reduce bubble errors. To verify the proposed design, a prototype ADC is implemented in a 0.18 µm process. Measurements at room temperature show that the SNDR and SFDR of the proposed prototype are 29.6 dB and 34.92 dB, with a resulting ENOB of 4.62 bits. It achieves an DNL and INL of +0.33 LSB /−0.54 LSB and +0.27 LSB/−0.33 LSB, respectively, and consumes 6 mW from a 1.8-V supply. At 0 °C and 60 °C, the ADC maintains a close performance.