Flash Analog-to-digital Converter Research Articles

Calibrating Amplifiers Nonlinearity Using Comparator-Based ADCs

Amplifiers are widely used within analog-to-digital converters (ADCs) to buffer and increase signal amplitude, alleviating the accuracy, noise, and power constraints of the ADCs. However, any nonlinearity caused by front-end amplifiers is fully or partially inherited by the ADC, compromising its overall linearity. Additionally, as CMOS processes scale, amplifiers become increasingly difficult to design due to reduced intrinsic gain and voltage headroom. Many applications rely on digital calibration to alleviate the amplifier specifications, which may use polynomial fitting or another sort of digital processing. Despite reducing the analog power, these solutions render high complexity and power consumption on the digital part. In this brief, we describe how comparator-based ADCs, such as a flash ADC or a comparator-based asynchronous binary search (CABS) ADC, inherently provide sufficient degrees of freedom to calibrate any monotonic nonlinearity. Then, we exploit this property to propose a low-complexity, low-power, and low-overhead calibration scheme, where we embed the inverse transfer function of the nonlinear amplifier into the decision thresholds of the following ADC. We also propose a statistical-driven algorithm that is used to guide the thresholds adjustment in the background. Finally, we extensively validate the proposed approach through behavioral simulations.

A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers

This paper presents a reference-free readout method for the phase-change memory (PCM) that compensates for the temperature drift of the cell resistance. The proposed method reconfigures the sense amplifier (SA) array into flash analog-to-digital converters (ADCs) in order to extract the optimum decision threshold for the given temperature from the distribution of the data output therefrom. The resolution of the reconfigured flash ADC, the number of flash ADCs for data averaging, and the required number of samples are determined for a target bit error rate of 1 ppm. The proposed SA drives a bit line (BL) rapidly with switchable current sources. A proof-of-concept prototype chip is fabricated via the 180-nm CMOS process. A single-channel readout path occupies $137 \times 27\,\,\mu \text{m}^{\mathbf {2}}$ and consumes $305~\mu \text{W}$ under a 3.3-V supply, with readout latency less than 100 ns.

Design of a high-sampling-rate electronic module for array-detector positron annihilation lifetime measurements

In this study, a high-time-resolution electronic module with a high channel density and low power consumption was designed for the measurement of the multi-detector array positron annihilation lifetimes. This electronic module consisted of 32 input channels, and each channel provided a high sampling rate up to 5.12 GSPS based on a Domino Ring Sampler 4 (DRS4) chip. Compared to the high-speed flash analog-digital converter (FADC), DRS4 chip has a higher channel density with an affordable lower price and power consumption. The developed electronic module was also capable of real-time data analysis for directly extracting the time information of input signals at the data acquisition site, thereby significantly decreasing the data rate. The digital constant fraction discriminator (DCFD) algorithm was implemented in the field programmable gate array (FPGA) for performing the time pick-up. The coincidence time resolution of the electronic module was measured, and the test results revealed a value of 26 ps. A prototypical 16-pixel detector module of the multi-detector system was evaluated using this electronic module, and the coincidence time resolution of the prototypical module was 411.84 ps. The electronic module was confirmed to satisfy the severe requirements of the multi-array-detector positron annihilation lifetime measurement system. It was also suitable for other high-time-resolution, high-channel-density, cost-effective, and low-power-consumption applications.

Time domain modelled ADC BIST with ramp noise projection

ABSTRACTThis paper proposes a time domain modelled built-in self-test (BIST) with ramp noise projection and their effects on analogue to digital converter (ADC) in testing. A self-biased linear ramp generator has been proposed for high precision testing. Threshold inversion quantization (TIQ) comparator based fast switching flash ADC has considered under test. A time domain model of output response analysis technique has been proposed to calibrate the linearity errors of the converter. An ADC has been validated with different input frequencies to characterize the harmonic distortion and average delay of the system. The proposed testing technique requires less time to measures the uncertainties of the ADC since the full computation is performed within one ramp cycle. The testing results of the proposed BIST technique are aimed to characterize, validate and compare to the best results of the existing ADC BIST techniques for test accuracy.

Error Detection of Data Conversion in Flash ADC using Code Width Based Technique

Abstract The high integration density of the complex electronic system requires the multi-functional testing facility to ensure the accuracy of the circuit function. In addition, the wide population of submicron technologies results in the persistent requirements of high precision analog and mixed-signal (AMS) circuits. In the complex, high-density circuits, observing the correctness of output are limited due to the limitations of input and output pins which develop the AMS circuit test as very difficult and expensive. A digital built-in self-test (BIST) scheme has been presented in this paper for testing an analog to digital converter (ADC) in the time domain. The testing scheme consists of the linear analog ramp generator, ADC as a circuit under test, output response analyzer and a BIST controller. Bootstrap linear ramp generator is used to generate the linear analog ramp signal which is applied to ADC to develop the digital word sequence for testing. Among various types of ADCs, here a Flash ADC has used since it is fastest and accurate in digital conversion. A Flash ADC has been designed with the seven-bit resolution and tested using the proposed digital BIST scheme. The ADC comprises a sample-hold circuit, 2N -1 comparator, XOR gates, and encoder block. The output response analyzer verifies the digital output sequence to validate the static test parameters of ADC called monotonicity, missing codes, DNL, and INL error. The BIST controller generates the control signals to control the test sequence. The complete test sequence of ADC BIST has simulated in Tanner EDA with TSMC 0.18um technology. ORA is used to analyze the presence of monotonicity, missing codes, DNL and INL error in the ADC output.

A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8<inline-formula> <tex-math notation="LaTeX">$\times$ </tex-math> </inline-formula> Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration

A 6-bit 2.5-GS/s $8\times $ dynamic interpolating flash analog-to-digital converter (ADC) with an offset calibration technique for interpolated voltage-to-time converters (VTCs) is presented for high-speed applications. The dynamic-amplifier-structured VTC enables linear zero-crossing (ZX) interpolation in the time domain with an interpolation factor of 8, which reduces the number of front-end VTCs to one-sixth the original structure. The reduced number of VTCs lowers the power consumption, load capacitance to the track-and-holder (T/H), and overhead of VTC offset calibration. The sequential slope-matching offset calibration scheme is proposed not only for VTC offset but also for interpolated ZX accuracy. The prototype 6-bit 2.5-GS/s flash ADC was implemented in a 65-nm CMOS process and occupies a 0.12 mm2 chip area, including offset calibration circuitry. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset calibration are 0.68 and 0.65 LSB, respectively. With a 1.23 GHz input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 33.84 and 45.07 dB, respectively, with power consumption of 7.5 mW under a supply voltage of 0.85 V. The prototype ADC achieves a figure of merit (FoM) of 74.7 fJ/conversion step at 2.5 GS/s.

A Biomedical Sensor System With Stochastic A/D Conversion and Error Correction by Machine Learning

This paper presents a high-precision biomedical sensor system with a novel analog-frontend (AFE) IC and error correction by machine learning. The AFE IC embeds an analog-to-digital converter (ADC) architecture called successive stochastic approximation ADC. The proposed ADC integrates a stochastic flash ADC (SF-ADC) into a successive approximation register ADC (SAR-ADC) to enhance its resolution. The SF-ADC is also used as a digitally controlled variable threshold comparator to provide error correction of the SAR-ADC. The proposed system also calibrates the ADC error using the machine learning algorithm on an external PC without additional power dissipation at a sensor node. Due to the flexibility of the system, the design complexity of an AFE IC can be relaxed by using these techniques. The target resolution is 18 bits, and the target bandwidth (without digital low-pass filter) is about 5 kHz to deal with several types of biopotential signals. The design is fabricated in a 130-nm CMOS process and operates at 1.2-V supply. The fabricated ADC achieves the SNDR of 88 dB at a sampling frequency of 250 kHz by using the proposed calibration techniques. Due to the high-resolution ADC, the input-referred noise is 2.52 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> with a gain of 28.5 dB.

Highly‐digital voltage scalable 4‐bit flash ADC

This study describes the highly-digital 4-bit 200 MS flash analogue to digital converter (ADC) whose major part can be digitally synthesised thus achieving low power, reducing the time-to-market and is scalable with technology. The comparators used in the ADC consist of complementary metal-oxide-semiconductor (CMOS)-based inverter and NAND-NOR as standard cells. The complete flash ADC is designed in 180 nm CMOS technology with 1.8 V supply with the power consumption of 4.51 mW. The signal-to-noise and distortion ratio, signal-to-noise ratio and spurious-free dynamic range are equal to 23.3, 25.2 and 30.1 dB. It provides an effective number of bits equal to 3.5. The differential non-linearity (DNL) of this ADC is ± 0.25 LSB and integral non-linearity (INL) is + 0.6 LSB.

A novel three-section encoder in a low-power 2.3 GS/s flash ADC

In this paper, as a novel, the encoder structure is divided into three sections. By using this method, each section has fewer number of inputs and outputs, hence simpler and less costly data conversion with less bubble errors and metastability will be obtained. In brief, the most significant bits (MSBs), the intermediate significant bits (ISBs) and the least significant bits (LSBs) are generated sequentially in a pipeline way and finally are latched by a latch bank. So, the flash analog-to-digital converter (ADC) with three-section encoder is more efficient than conventional ones, especially in high-speed and high-resolution conditions. A 6-bit 2.3 GS/s flash ADC is simulated that achieves the figure of merit (FOM) of 0.146 pJ/conversion-step and consumes 20.56 mW from a 1.2 V supply voltage.

Design and implementation of reliable flash ADC for microwave applications

Analog to Digital Converter (ADC) is a necessary component of mixed signal designs. It converts the analog signal to the digital signal so that it is used as a bridge. This paper proposes R-Flash ADC (Reliable Flash ADC) which combines an area efficient multiplexer pass gate (MPG) encoding technique and low power ITIQ (Improved Threshold Inverter Quantization) comparator. The proposed Flash ADC is implemented using tanner EDA with 125 nm technology. R-Flash ADC reduces the number of transistors by 39% and reduces the power consumption by 59% with high resolution quality when compared to Mux TIQ ADC. The reliability analysis shows that the proposed R-Flash ADC has reliability of 95% and it overcomes the existing techniques as well.

A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC

In this paper, we propose a time-based analog-to-digital converter (ADC) architecture combining a flash ADC and vernier time-to-digital converter (TDC) to achieve both high speed and high resolution. The flash ADC and vernier TDC are pipelined to increase the conversion speed. A charge-steering amplifier is used for low-power residue transfer. A common level adjuster is added to the output stage of the charge-steering amplifier to stabilize the output common level against process, voltage, and temperature variation. Moreover, the vernier TDC using a dynamic delayer enables low-power operation. An 8-bit ADC test chip fabricated with 65-nm CMOS technology had a high sampling frequency (900 MHz) and low power consumption (3.5 mW). The figure of merit was 32 fJ/conversion step.

Implementation of Low Power Programmable Flash ADC Using IDUDGMOSFET

In this brief, a novel programmable low power analog-to-digital converter (ADC) circuit design is proposed using independently driven underlap double gate MOSFET (IDUDGMOS) to operate in radio frequency domain and its performance is studied. The primary motivation of the design is to eliminate the need for a resistor ladder for reference voltage selection and to minimize the number of transistor used in the flash ADCs. The proposed design utilizes the back gate voltage controllability of IDUDGMOS for varying reference voltage of the comparators in the ADCs. The parameters of the designed ADC analyzed are the bandwidth, the linearity, and the power consumption of the circuit. The proposed circuit offers wider bandwidth and lower power consumption compared to earlier ADC designs.

A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link

A 0.88 mm2 65-nm analog-to-digital converter (ADC)-based serial link transceiver is designed with a maximum-likelihood sequence detector (MLSD) for robust equalization. The MLSD is optimized in a pipelined look-ahead architecture to reach 10 Gb/s at 5.8 pJ/b and 5 Gb/s at 3.9 pJ/b, making it practical for an energy-efficient ADC-based serial link. Compared with linear equalizer and decision feedback equalizer, the MLSD provides extra margin to accommodate timing offsets, ADC nonlinearities, and voltage noise, which is exploited by co-designing the analog front-end to reduce its power and area. We present a 2x-oversampled and 2-way interleaved 5 b stochastic flash ADC architecture. No front-end analog equalizer, buffer or sample, and hold amplifier are needed. Tested with a 45-cm FR-4 trace, the serial link transceiver achieves 5 Gb/s at a bit error rate below 10−11 with a 7% UI margin without any analog front-end equalization, consuming 54.5 mW in receiver and 16.2 mW in transmitter.

A 39.5-dB SNR, 300-Hz Frame-Rate, 56 × 70-Channel Read-Out IC for Electromagnetic Resonance Touch Panels

In this paper, a pen detection analog system for an electromagnetic resonance (EMR) touch panel is presented. An adaptive charge pump is proposed in the transmitter to drive a high current to the EMR panel and achieve a high signal-to-noise ratio (SNR) in the receiver. To compensate for the mismatches between the channels due to fabrication variations of the EMR panels and process variations of the analog front-ends (AFEs), a transmitter driver with an adaptive controller is proposed, and an AFE calibration is implemented in the transmitter and the receiver, respectively. Also, a 9-bit, 2-MS/s time-interleaved flash successive-approximation-register (SAR) analog-to-digital converter (ADC) with 3-bit flash and 6-bit SAR ADCs is proposed to increase the frame rate with small area and power consumption. External noises, such as display and charger noises, can be rejected by the differential processing, analog low-pass filter, and digital filters in the digital signal processor (DSP). This read-out integrated circuit is implemented in a 0.18-μm Bipolar-CMOS-DMOS (BCD), and the die area is ${\text{40 mm}}^{\text{2}}$ including DSP and ADCs. The power consumptions are 110 and 45 mW in the transmitter and receiver modes, respectively. The SNR is about 39.5 dB and the frame rate is about 300 Hz in the 56 × 70 touch panel.

A 14b 250MSps Pipelined ADC with Digital Self‐calibration in 0.18µm CMOS Process

A 14-bit pipelined Analog-to-digital converter (ADC) with a single-side digital self-calibration in a 0.18μm CMOS process is presented. The single-side foreground digital self-calibration is introduced to reduce the nonlinearity caused by capacitor mismatches. The ADC has a front-end Sample-and-hold (SH) circuit, followed by 13 1.5bit/stage sub-ADC and 2bit flash ADC at last. Test results show that, with a 140MHz input and 200MHz sampling rate, the SIAND is improved from 59dB to 66dB and SFDR is improved from 62dBc to 82dBc with the digital calibration. The measured SFDR reaches 77dBc even at 250MSps after calibration. The total power dissipation is 398mW at 250MSps including the parallel Low voltage differential signal (LVDS) output drivers.

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6–8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.

A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS

A non-interleaved 2-GS/s, 8-bit flash analog-to-digital converter (ADC) utilizing the remainder number system (RNS) quantization principle is presented. The RNS quantization reduces the number of comparators and thus improves the figure of merit of the flash ADC. A time-domain implementation is adopted to reduce the ADC input capacitance with a voltage-to-time converter (VTC) front end. The ring oscillator-based time-to-digital converter (TDC) also provides a linear and efficient modulo (folding) operation for the RNS quantization with built-in dynamic element matching. Offline TDC mismatch calibration based on a histogram (code density) test is also employed to further improve the ADC linearity. The prototype RNS ADC was fabricated in a 65-nm CMOS process with an active area of 0.08 mm2. It measures an SNDR of 40.7 dB for a Nyquist input and an effective resolution bandwidth of 1.74 GHz.

Channel-Adaptive ADC and TDC for 28 Gb/s PAM-4 Digital Receiver

A low-power channel-adaptive 28 Gb/s PAM-4 receiver is presented utilizing a predictive analog-to-digital converter (ADC), a successive-approximation-register (SAR) time-to-digital converter (TDC), and a feed-forward equalizer (FFE) in the digital domain. The variable-resolution flash ADC takes advantage of the channel inter-symbol interference (ISI) and can achieve 5.5 bits resolution utilizing only 16 comparators. By reusing the comparators, the ADC can provide a programmable resolution from 2 to 5.5 bits consuming 40 to 90 mW, respectively. The SAR-TDC generates 5 bits timing information that includes 2 bits ISI and 3 bits timing error to achieve a low-latency and low-jitter timing recovery. Subsequently, a three-to-eight programmable tap FFE is used to equalize up to 30-dB loss achieving bit error rate lower than 10−8. FFE is implemented in a field-programmable gate array, and the first three taps are realized in a look-up table (LUT). An offline higher resolution ADC is used to generate the pre-computed values for the LUT. Measured power consumption is 130 mW (excluding digital signal processing) from a 1.2-V power supply with active chip area of 0.2025 mm2 in 65-nm technology. Due to programmability on the both ADC resolution and the number of FFE taps according to the channel loss, the receiver enables energy efficiency according to loss compensation.

Susceptibility of flash ADCs to electromagnetic interference

Integrated devices acquiring environmental, industrial or biomedical signals are ubiquitous and require sensor systems to be situated in electromagnetically hostile environments and continue to operate reliably. The susceptibility to injected electromagnetic interference by an 8-bit flash Analog to Digital Converter (ADC) was measured using the direct power injection method (IEC 62132-4). The analysis of the immunity results and the susceptibility of the internal structure of the device are presented. Measurements show that the supply port is immune to interference but the analog input and reference voltage input ports are quite susceptible. Better understanding of the susceptibility of a flash ADC to EMI enables designers to reduce the cost of preventative measures implemented at the system level and improve the reliability of sensor systems.

Six‐bit, reusable comparator stage‐based asynchronous binary‐search SAR ADC using smart switching network

A reusable comparator stage-based asynchronous binary-search Successive Approximation Register (SAR) analogue-to-digital converter (ADC) with a smart reference range prediction network is presented in this brief. The proposed architecture has an advantageous merit of using only N comparators in comparison with original binary-search ADC and flash ADC. The design uses selection logic which selects and activates the comparator one at a time, and a smart switching network which allocates reference voltage to selected comparators in the successive comparison process. It claims for equipoise with power and operating speed when compared with flash ADC and SAR ADC. The post-layout simulated performance of 6 bit conversion using only six comparators on United Microelectronics Corporation (UMC)-180 nm achieves 41 dB spurious-free dynamic range and 36.02 dB signal-to-noise distortion ratio with a maximum sampling speed of 330 MS/s consuming 0.64 mW power when operated at 1.8 V supply, corresponding figure-of-merit 36.47 fJ/conversion step.