A novel three-section encoder in a low-power 2.3 GS/s flash ADC

Abstract

In this paper, as a novel, the encoder structure is divided into three sections. By using this method, each section has fewer number of inputs and outputs, hence simpler and less costly data conversion with less bubble errors and metastability will be obtained. In brief, the most significant bits (MSBs), the intermediate significant bits (ISBs) and the least significant bits (LSBs) are generated sequentially in a pipeline way and finally are latched by a latch bank. So, the flash analog-to-digital converter (ADC) with three-section encoder is more efficient than conventional ones, especially in high-speed and high-resolution conditions. A 6-bit 2.3 GS/s flash ADC is simulated that achieves the figure of merit (FOM) of 0.146 pJ/conversion-step and consumes 20.56 mW from a 1.2 V supply voltage.