Performance evaluation of a new single-ended comparator for low-power high-speed flash ADC

Abstract

ABSTRACTIn this paper, a new single-ended comparator is explored for designing the reference ladder-free flash analog-to-digital converter (ADC). This proposed comparator generates inherent embedded threshold voltage. It uses the variable threshold voltage-generation method for producing the reference voltage for the flash ADC design. Employing optimised comparator gives various benefits, as it does not require the necessity of a reference resistor ladder as well as front-end track and hold circuit. This reduces both layout area and power consumption and makes it appropriate for system-on-chip ADC implementation. The basic structure of the single-ended comparator is a modified complementary metal oxide semiconductor (CMOS) inverter. The performance of the modified CMOS inverter circuit is compared with the CMOS inverter. Simulation results show that the modified CMOS inverter-based comparator achieves average power consumption of 1.46 μW with propagation delay of 53.8 ps. To demonstrate the functionality of the new comparator, a 4-bit flash ADC has also been realised. The designed 4-bit flash ADC exhibits significant improvement in terms of power and speed of previously reported flash ADCs. The converter consumes power 274 μW from a 1.8-V supply and achieves the conversion speed of 1 GHz in United Microelectronics Corporation 180-nm CMOS. The measurement of maximum differential and integral nonlinearities of the flash ADC are 0.2 least significant bit (LSB) and 0.6 LSB, respectively.