A novel low bias and high speed non-classical CMOS inverter with unique shared contact

Abstract

We propose a novel non-classical complementary metal oxide semiconductor (CMOS) inverter, which is composed of a Gated control NNP for driver N-type transistor (Gated-NNP) and a Gated control PPN for load P-type transistor (Gated-PPN). These two transistors have the same doping architecture with tunnel field effect transistor (TFET), but not use tunneling current mechanisms to achieve complementary characteristics. Our Gated-NNP/PPN CMOS inverter exhibits the propagation delay time (TP) 55% lower than the conventional CMOS inverter. Besides, the layout area of the novel inverter is significantly reduced about 46.1% when compared with the conventional CMOS inverter due to the new inverter possesses a unique shared-contacting output node.