Abstract

In this paper, a 3-bit hybrid spin-CMOS Flash analog to digital converter (ADC) is developed, which works based on switching of perpendicular-anisotropy magnetic tunnel junctions (p-MTJs) using both spin Hall effect (SHE) and spin-transfer torque (STT). The structure consists of unconnected p-MTJs in which heavy metals (HMs) are implemented with different cross-sectional areas leading to devices with different critical current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</inf> ) values. I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</inf> values act as reference currents (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</inf> ) eliminating the need for transistors with different sizes creating various values of I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</inf> . Moreover, the power-hungry comparators in complementary metal-oxide-semiconductor (CMOS) Flash ADC can be replaced with p-MTJs because they compare the input current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</inf> ) with their I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</inf> . Hence, this approach can reduce the chip area and the mismatch issue as compared to the conventional CMOS Flash ADC. In this structure, a copy of Iin passes through the HM of each p-MTJ, which improves the tunnel magnetoresistance (TMR) and as a results increasing the reading reliability, linearity, and speed of spin Hall-based ADCs with attached HMs. The simulation results in 180nm CMOS technology show 845 μW of power consumption at 200 MS/s with the differential nonlinearity (DNL) and integral nonlinearity (INL) of -0.149 LSB (least significant bit) and 0.085 LSB, respectively.

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