A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8<inline-formula> <tex-math notation="LaTeX">$\times$ </tex-math> </inline-formula> Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration

Abstract

A 6-bit 2.5-GS/s $8\times $ dynamic interpolating flash analog-to-digital converter (ADC) with an offset calibration technique for interpolated voltage-to-time converters (VTCs) is presented for high-speed applications. The dynamic-amplifier-structured VTC enables linear zero-crossing (ZX) interpolation in the time domain with an interpolation factor of 8, which reduces the number of front-end VTCs to one-sixth the original structure. The reduced number of VTCs lowers the power consumption, load capacitance to the track-and-holder (T/H), and overhead of VTC offset calibration. The sequential slope-matching offset calibration scheme is proposed not only for VTC offset but also for interpolated ZX accuracy. The prototype 6-bit 2.5-GS/s flash ADC was implemented in a 65-nm CMOS process and occupies a 0.12 mm2 chip area, including offset calibration circuitry. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset calibration are 0.68 and 0.65 LSB, respectively. With a 1.23 GHz input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 33.84 and 45.07 dB, respectively, with power consumption of 7.5 mW under a supply voltage of 0.85 V. The prototype ADC achieves a figure of merit (FoM) of 74.7 fJ/conversion step at 2.5 GS/s.