Fixed-point Arithmetic Research Articles

A Parameterized Floating-Point Formalizaton in HOL Light

We present a new, open-source formalization of fixed and floating-point numbers for arbitrary radix and precision that is now part of the HOL Light distribution [John Harrison. HOL Light: A tutorial introduction. In Formal Methods in Computer-Aided Design, pages 265–269. Springer, 1996]. We prove correctness and error bounds for the four different rounding modes, and formalize a subset of the IEEE 754 [IEEE standard for floating point arithmetic. IEEE Std. 754-2008, 2008] standard by gluing together a set of fixed-point and floating-point numbers to represent the subnormals and normals. In our floating-point proofs, we treat phases of floating-point numbers as copies of fixed-point numbers of varying precision so that we can reuse fixed-point rounding theorems.

Cost-efficient FPGA implementation of basal ganglia and their Parkinsonian analysis

The basal ganglia (BG) comprise multiple subcortical nuclei, which are responsible for cognition and other functions. Developing a brain–machine interface (BMI) demands a suitable solution for the real-time implementation of a portable BG. In this study, we used a digital hardware implementation of a BG network containing 256 modified Izhikevich neurons and 2048 synapses to reliably reproduce the biological characteristics of BG on a single field programmable gate array (FPGA) core. We also highlighted the role of Parkinsonian analysis by considering neural dynamics in the design of the hardware-based architecture. Thus, we developed a multi-precision architecture based on a precise analysis using the FPGA-based platform with fixed-point arithmetic. The proposed embedding BG network can be applied to intelligent agents and neurorobotics, as well as in BMI projects with clinical applications. Although we only characterized the BG network with Izhikevich models, the proposed approach can also be extended to more complex neuron models and other types of functional networks.

Multiplicative finite impulse response filters: implementations and applications using field programmable gate arrays

This paper describes how modern field programmable gate array (FPGA) technology can be used to build practical and efficient multiplicative finite impulse response (MFIR) filters with low-pass, high-pass, band-pass and band-stop characteristics. This paper explains how MFIR structures can be built with or without linear phase characteristics and implemented efficiently on modern FPGA architectures using fixed-point arithmetic without incurring stability problems or limit cycles which commonly occur when using equivalent infinite impulse response structures. These properties have a particular importance for applications such as tunable resonators, narrow band rejectors and linear phase filters which have demanding, narrow transition band requirements. The results presented in this paper indicate that MFIR filters are, for some applications, a viable alternative to existing filter structures when implemented on an FPGA.

Slow thinking and deep learning: Tversky and Kahneman's taxi cabs

SummaryThis article is based on classroom application of a problem story constructed by Amos Tversky in the 1970s. His intention was to evaluate human beings' intuitions about statistical inference. The problem was revisited by his colleague, the Nobel Prize winner Daniel Kahneman. The aim of this article is to show how popular science textbooks can serve as a source for rich classroom activity, with a little care in the implementation by teachers. Kahneman describes the problem as ‘standard’ and answers using a fixed point number. I describe how I have encouraged my students to challenge the certainty of this assertion by identifying ambiguities that are left unexplained in the story. This way, I claim to stimulate individuals to indeed move towards Thinking, Fast and Slow, the title of Kahneman's book.

Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications

The need to support various digital signal processing (DSP) and classification applications on energy-constrained devices has steadily grown. Such applications often extensively perform matrix multiplications using fixed-point arithmetic while exhibiting tolerance for some computational errors. Hence, improving the energy efficiency of multiplications is critical. In this brief, we propose multiplier architectures that can tradeoff computational accuracy with energy consumption at design time. Compared with a precise multiplier, the proposed multiplier can consume 58% less energy/op with average computational error of $\sim 1$ %. Finally, we demonstrate that such a small computational error does not notably impact the quality of DSP and the accuracy of classification applications.

Energy‐efficient low bit rate image compression in wavelet domain for wireless image sensor networks

The problem related to energy conservation in a resource-constrained wireless visual sensor network applied for habitat monitoring, border patrol, battlefield surveillance and so on, where images have to be transmitted over a wireless medium with limited bandwidth, is addressed. The proposed approximation band transform algorithm is unique and novel since it extracts and encodes only approximations of the image using fixed-point arithmetic without applying highpass analysis filters. This low bit rate image compression algorithm is specifically designed for resource-constrained low-power sensors. Its performance is analysed in terms of bit rate (bits per pixel), image quality, processing time and its energy consumption in an Atmel Atmega128 processor. It is shown that this algorithm consumes only 12% of energy needed by joint photographic experts group (JPEG) [independent JPEG group (IJG)] version and gives better results than JPEG at very low bit rates and thus the proposed scheme can significantly enhance the lifetime of low-power sensors.

A General Framework for FPGA-Based Real-Time Emulation of Electrical Machines for HIL Applications

Hardware-in-the-loop (HIL) technology is increasingly becoming the preferred, reliable, and cost-effective alternative in a virtual scenario for tedious, time-consuming, and expensive tests on real devices. This paper presents a digital hardware emulation of commonly used electrical machines for HIL simulation on the field-programmable gate arrays (FPGAs) in a general framework. This paper provides a useful and comprehensive comparison between floating- and fixed-point arithmetic for hardware implementation, and addresses the differences of deeply pipelined and highly paralleled realization schemes, and the contribution of schematic and textual programming language methods for design configuration of electrical machine models. The hardware implementation by these approaches is evaluated in terms of real-time step size, accuracy, and hardware resource consumption. Finally, an experimentally measured electrical machine behavior is employed to demonstrate the effectiveness of the emulated electrical machine.

A dual gradient-projection algorithm for model predictive control in fixed-point arithmetic

Although linear Model Predictive Control has gained increasing popularity for controlling dynamical systems subject to constraints, the main barrier that prevents its widespread use in embedded applications is the need to solve a Quadratic Program (QP) in real-time. This paper proposes a dual gradient projection (DGP) algorithm specifically tailored for implementation on fixed-point hardware. A detailed convergence rate analysis is presented in the presence of round-off errors due to fixed-point arithmetic. Based on these results, concrete guidelines are provided for selecting the minimum number of fractional and integer bits that guarantee convergence to a suboptimal solution within a pre-specified tolerance, therefore reducing the cost and power consumption of the hardware device.

A Low Complexity Scaling Method for the Lanczos Kernel in Fixed-Point Arithmetic

We consider the problem of enabling fixed-point implementation of linear algebra kernels on low-cost embedded systems, as well as motivating more efficient computational architectures for scientific applications. Fixed-point arithmetic presents additional design challenges compared to floating-point arithmetic, such as having to bound peak values of variables and control their dynamic ranges. Algorithms for solving linear equations or finding eigenvalues are typically nonlinear and iterative, making solving these design challenges a nontrivial task. For these types of algorithms, the bounding problem cannot be automated by current tools. We focus on the Lanczos iteration, the heart of well-known methods such as conjugate gradient and minimum residual. We show how one can modify the algorithm with a low-complexity scaling procedure to allow us to apply standard linear algebra to derive tight analytical bounds on all variables of the process, regardless of the properties of the original matrix. It is shown that the numerical behavior of fixed-point implementations of the modified problem can be chosen to be at least as good as a floating-point implementation, if necessary. The approach is evaluated on field-programmable gate array (FPGA) platforms, highlighting orders of magnitude potential performance and efficiency improvements by moving form floating-point to fixed-point computation.

Reducing the computational footprint for real-time BCPNN learning.

The implementation of synaptic plasticity in neural simulation or neuromorphic hardware is usually very resource-intensive, often requiring a compromise between efficiency and flexibility. A versatile, but computationally-expensive plasticity mechanism is provided by the Bayesian Confidence Propagation Neural Network (BCPNN) paradigm. Building upon Bayesian statistics, and having clear links to biological plasticity processes, the BCPNN learning rule has been applied in many fields, ranging from data classification, associative memory, reward-based learning, probabilistic inference to cortical attractor memory networks. In the spike-based version of this learning rule the pre-, postsynaptic and coincident activity is traced in three low-pass-filtering stages, requiring a total of eight state variables, whose dynamics are typically simulated with the fixed step size Euler method. We derive analytic solutions allowing an efficient event-driven implementation of this learning rule. Further speedup is achieved by first rewriting the model which reduces the number of basic arithmetic operations per update to one half, and second by using look-up tables for the frequently calculated exponential decay. Ultimately, in a typical use case, the simulation using our approach is more than one order of magnitude faster than with the fixed step size Euler method. Aiming for a small memory footprint per BCPNN synapse, we also evaluate the use of fixed-point numbers for the state variables, and assess the number of bits required to achieve same or better accuracy than with the conventional explicit Euler method. All of this will allow a real-time simulation of a reduced cortex model based on BCPNN in high performance computing. More important, with the analytic solution at hand and due to the reduced memory bandwidth, the learning rule can be efficiently implemented in dedicated or existing digital neuromorphic hardware.

Вопросы реализации на целочисленной ЦВС (типа «Малахит-3») алгоритма тарировки датчиков БИНС в полете по информации от высокоточной ИНС

The paper is devoted to the formulation of the problem for vector matching for strapdown inertial navigation system (SINS), allows to gauge gyro and accelerometer sensors of SINS, and to the problems of realization an vector matching algorithm on digital computing system (DCS), which operates with a fixed point number, an example of which is the DCS “Malachite-3”. The results of mathematical modeling for gauging 4 gyro sensors of SINS, based on a fiber optic gyroscope, via vector matching with the high-precision inertial navigation system, based on the gyroscopestabilized platform, are presented. The results of algorithm realization for vector matching on DCS “Malachite-3” with 32-bit arithmetic are presented. Also presented the estimated time required for computation of the algorithm.

VLSI Implementation of Lattice Wave Digital Filters Using Fixed Point Arithmetic for Increased Maximum Sampling Frequency

VLSI Implementation of Lattice Wave Digital Filters Using Fixed Point Arithmetic for Increased Maximum Sampling Frequency Low complexity and high speed are the key requirements of the digital filters. These filters can be realized using all-pass sections. In this paper, design and minimum hardware implementation of a fixed point lattice wave digital filter based on three port series adaptor is proposed. Here, the second-order all-pass sections are replaced with three port series adaptors. A design-level area optimization is done by converting constant multipliers into shifts and adds using canonical signed digit (CSD) techniques. The proposed implementation reduces the latency of the critical loop by reducing the number of components (adders and multipliers).

Experimental Demonstration Of The Fixed-Point Sparse Coding Performance

Abstract The Sparse Coding (SC) model has been proved to be among the best neural networks which are mainly used in unsupervised feature learning for many applications. Running a sparse coding algorithm is a time-consuming task due to its large scale and processing characteristics, which naturally leads to investigating FPGA acceleration. Fixed-point arithmetic can be used when implementing SC in FPGAs to reduce the execution time, but the implications for accuracy are not clear. Previous studies have focused only on accelerators using some fixed bitwidths on other neural networks models. Our work gives a comprehensive evaluation to demonstrate the bit-width effect on SCs, achieving the best performance and area efficiency. The method of data format conversion and the matrix blocking are the main factors considered according to the situation of hardware implementation. The simulation method of the simple truncation, the representation of the domain constraint and the matrix blocking with different parallelism were evaluated in this paper. The results have shown that the fixedpoint bit-width did have effect on the performance of SC. We must limit the representation domain of the data carefully and select an available bit-width according to the computation parallelism. The result has also shown that using a fixed-point arithmetic can guarantee the precision of the SC algorithm and get acceptable convergence speed.

Embedded Online Optimization for Model Predictive Control at Megahertz Rates

Faster, cheaper, and more power efficient optimization solvers than those currently possible using general-purpose techniques are required for extending the use of model predictive control (MPC) to resource-constrained embedded platforms. We propose several custom computational architectures for different first-order optimization methods that can handle linear-quadratic MPC problems with input, input-rate, and soft state constraints. We provide analysis ensuring the reliable operation of the resulting controller under reduced precision fixed-point arithmetic. Implementation of the proposed architectures in FPGAs shows that satisfactory control performance at a sample rate beyond 1 MHz is achievable even on low-end devices, opening up new possibilities for the application of MPC on embedded systems.

Multiscale matched filter-based lane detection scheme of the constant false alarm rate for driver assistance

Real-time lane detection is an important element for driver assistance systems in rapidly changing traffic scenarios. In this paper, an embedded lane detection platform combining a high-dynamic-range image sensor is proposed. As for the software development, a multiscale matched filter scheme is successfully used to enhance the local contrast between the lane markings and the background interference for different traffic scenarios. Then, an intelligent constant-false-alarm-rate detector is designed to generate an adaptive threshold for extraction of the lane markings. As for hardware implementation, a field programmable gate array is used for obtaining a high-dynamic-range image, and then matched filters achieve their optimal design based on the coefficient decomposition technology in the form of a fixed point number. Subsequently, through a high-speed serial peripheral interface bus, all pre-processed data are transferred to an ARM processor, which takes charge of extraction of the lane markings and also lane fitting. Experiments and evaluation prove that the proposed system can effectively detect the lane markings for different traffic scenarios in a time of 11.64 ms for each frame.

A Fast and Accurate Orthorectification Algorithm of Aerial Imagery Using Integer Arithmetic

In the past decade, imaging systems have increased in size and quality while decreasing in cost. As the cost has decreased, many aerial imaging applications have become practical such as tracking, vegetation indexing, coast line monitoring, etc. However, many of these applications require geo-location and orthorectification to enable analysis. Orthorectification is a computationally expensive process due to floating-point operations and divisions in the algorithm. To reduce the computational cost of on-board processing, two novel algorithm modifications are proposed. One modification is projection utilizing fixed-point arithmetic. Fixed-point arithmetic removes the floating-point operations and reduces the processing time by operating only on integers. The second modification is replacement of the division inherent in projection with a multiplication of the inverse. With these modifications, the processing time of the projection is reduced by a factor of 1.2 × with an average pixel position error of 0.5% of a pixel size for 128-bit integer processing and over 2 × with an average pixel position error of less than 15% of a pixel size for a 64-bit integer processing.

Flexible design of wide‐pipeline‐based WiMAX QC‐LDPC decoder architectures on FPGAs using high‐level synthesis

A novel wide-pipeline low-density parity-check (LDPC) decoder approach for the worldwide interoperability for microwave access (WiMAX) standard (802.16e) is proposed for execution on field-programmable gate arrays (FPGAs), using a high-level synthesis tool to reduce the development effort and design validation time that generates a wide-pipeline architecture. Optimised open computing language (OpenCL)-based kernels are developed and the integration of distinct configurations of single instruction multiple data and compute units to increase the level of parallelism are analysed. The decoding throughput surpasses the minimal requirements of 75 Mbit/s, a key figure of merit that ranks the design with other very large-scale integration-based approaches. Furthermore, extra precision is deployed with 8-bit fixed-point arithmetic, delivering superior bit error rate performance and lower error floor regions.

Options for Denormal Representation in Logarithmic Arithmetic

Economical hardware often uses a FiXed-point Number System (FXNS), whose constant absolute precision is acceptable for many signal-processing algorithms. The almost-constant relative precision of the more expensive Floating-Point (FP) number system simplifies design, for example, by eliminating worries about FXNS overflow because the range of FP is much larger than FXNS for the same wordsize; however, primitive FP introduces another problem: underflow. The Signed Logarithmic Number System (SLNS) offers similar range and precision as FP with much better performance (in terms of power, speed and area) for multiplication, division, powers and roots. This paper proposes three variations of a new number system, respectively called the Denormal LNS (DLNS), Denormal Mitchell LNS (DMLNS) and Denormal Offset Mitchell LNS (DOMLNS), which are all hybrids of the properties of FXNS and SLNS. The inspiration for D(OM)LNS comes from the denormal (aka subnormal) numbers found in IEEE-754 (that provide better, gradual underflow) and the μ-law often used for speech encoding; the novel DLNS circuit here allows arithmetic to be performed directly on such encoded data. The proposed approach allows customizing the range in which gradual underflow occurs. Our first DLNS implementation leverages existing SLNS basic blocks. Synthesis shows the novel circuit primarily consists of traditional SLNS addition and subtraction tables, with additional datapaths that allow the novel arithmetic unit to act on conventional SLNS as well as DLNS and mixed data, for a worst-case area overhead of 26 %. Unlike SLNS, this DLNS implementation is still costly for general (non-constant) multiplication, division and roots. To overcome this difficulty, this paper proposes the other variations called Denormal Mitchell LNS (DMLNS) and Denormal Offset Mitchell LNS (DOMLNS), in which the well-known Mitchell’s method makes the cost of general multiplication, division and roots closer to that of SLNS. Taylor-series computations suggest subnormal values in DMLNS and DOMLNS also behave similarly to those in the IEEE-754 FP standard. Synthesis shows that DMLNS and DOMLNS respectively have average area overheads of 25 % and 17 % compared to an equivalent SLNS 5-operation unit.

Speeding up deep neural network based speech recognition systems

Recently, deep neural network (DNN) based acousticmodeling has been successfully applied to largevocabulary continuous speech recognition (LVCSR) tasks.A relative word error reduction around 20% can beachieved compared to a state-of-the-art discriminativelytrained Gaussian Mixture Model (GMM). However, due tothe huge number of parameters in the DNN, real-time decodingis a bottleneck for the DNN based speech recognitionsystems. In this paper, we adopt several techniques for thespeed optimization of the DNN-based system. Specifically,we use singular value decomposition (SVD) to reduce themodel parameters, use the SSE instruction sets for theparallel calculation in the data space, and quantize themodel parameters reasonably to convert the floating-pointarithmetic into fixed-point arithmetic. Besides, taking thecharacteristics of speech signal into account, we use a frameskippingmethod when evaluating the posterior probabilities.Finally, compared to the un-optimized baseline system, withnegligible recognition performance loss, the decoding realtimefactor of the optimized one is significantly reduced,from 6.1 to 0.31. And this response speed can basically meetthe requirement of our real applications.

A Novel Strategy for Proficient Channel Limitation Equalizer

A time-domain equalizer (TEQ) employed in cascade with the channel yields an actual impulse response that is squatter than the channel impulse response. Time-domain equalization is critical in reducing channel state dimension in maximum likelihood sequence approximation, and inter-carrier and inter-symbol interference in multicarrier systems. This project evaluates two TEQ design methods docile to cost-effective real-time implementation: least mean squared error (LMSE) and extreme shortening SNR (ESSNR) methods. We condense the complexity of computing the matrices in the ESSNR and LMSE designs by a factor of 140 and a factor of 16 (respectively) relative to existing approaches, without degrading performance. We prove that an infinite length ESSNR TEQ with unit norm TEQ constraint is symmetric. A symmetric TEQ halves FIR implementation density, enables parallel training of the frequency-domain equalizer and TEQ, reduces TEQ training complexity by a factor of 4 and doubles the length of the TEQ that can be designed using fixed-point arithmetic, with only a small loss in bit rate. Simulations are presented for designs with a symmetric TEQ or target impulse response.