Fixed-point Arithmetic Research Articles

An algorithm for compact fixed-point implementation of digital controllers

We propose and study the algorithm of digital controllers implementation in fixed-point arithmetic based on the adaptive selection of a discrete transform and a discrete operator (z- or δ-operator). An experimental verification of the proposed criteria for the transform and operator selection is performed, also results of the proposed algorithm testing are given. Suggested approach made it possible to reduce the number of utilized logic elements in the FPGA or ASIC implementation of controllers up to 2-3 times and more in comparison with the traditional technique based on the application of the Tustin transform and z-operator, and also reduce the development complexity. The obtained results are of practical importance in the electronic units design for autonomous embedded systems, space vehicles and other objects with restricted mass, dimensions and power consumption, giving the possibility to overcome these restrictions.

Temperature estimation of induction machines based on wireless sensor networks

Abstract. In this paper, a fourth-order Kalman filter (KF) algorithm is implemented in the wireless sensor node to estimate the temperatures of the stator winding, the rotor cage and the stator core in the induction machine. Three separate wireless sensor nodes are used as the data acquisition systems for different input signals. Six Hall sensors are used to acquire the three-phase stator currents and voltages of the induction machine. All of them are processed to root mean square (rms) in ampere and volt. A rotary encoder is mounted for the rotor speed and Pt-1000 is used for the temperature of the coolant air. The processed signals in the physical unit are transmitted wirelessly to the host wireless sensor node, where the KF is implemented with fixed-point arithmetic in Contiki OS. Time-division multiple access (TDMA) is used to make the wireless transmission more stable. Compared to the floating-point implementation, the fixed-point implementation has the same estimation accuracy at only about one-fifth of the computation time. The temperature estimation system can work under any work condition as long as there are currents through the machine. It can also be rebooted for estimation even when wireless transmission has collapsed or packages are missing.

Theoretical Study of the One Self-Regulating Gene in the Modified Wagner Model

Predicting how a genetic change affects a given character is a major challenge in biology, and being able to tackle this problem relies on our ability to develop realistic models of gene networks. However, such models are rarely tractable mathematically. In this paper, we propose a mathematical analysis of the sigmoid variant of the Wagner gene-network model. By considering the simplest case, that is, one unique self-regulating gene, we show that numerical simulations are not the only tool available to study such models: theoretical studies can be done too, by mathematical analysis of discrete dynamical systems. It is first shown that the particular sigmoid function can be theoretically investigated. Secondly, we provide an illustration of how to apply such investigations in the case of the dynamical system representing the one self-regulating gene. In this context, we focused on the composite function f a ( m . x ) where f a is the parametric sigmoid function and m is a scalar not in { 0 , 1 } and we have proven that the number of fixed-point can be deduced theoretically, according to the values of a and m.

Self-reconfigurable implementation for a switched beam smart antenna

We present a self-reconfigurable embedded system for a switched beam smart antenna that can steer the beam pattern into a desired direction, handle arithmetic overflow, and respond to user-specified constraints on accuracy and resources. The main component (adaptive beamforming) is implemented as a fully customized hardware in fixed-point arithmetic. By varying the numerical formats and desired beam patterns, we generate a set of hardware configurations, which can then be selected at run-time via a dynamic manager implemented in software. The self-reconfigurable embedded system is implemented and tested on a Programmable System-on-Chip (PSoC). Results are presented in terms of resources, accuracy, and run-time hardware adaptation. This work illustrates the benefits of run-time reconfiguration technology on PSoCs for the implementation of switched-beam smart antennas.

Stability analysis of digital filters subjected to interference using generalized overflow nonlinearities

In this paper, we feature a new criterion using an input–output-to-state stability (IOSS) approach for digital filters employing fixed-point arithmetic with generalized overflow nonlinearities in the presence of external disturbances. The proposed linear matrix inequality (LMI)-based criterion eliminates the presence of limit cycles and ensures not only the IOSS of digital filters but also their asymptotic stability when external interference is exhausted. Through several numerical examples, the effectiveness of the proposed criterion is illustrated, and it is shown that it covers a broad class of nonlinearities, namely saturation, zeroing, two's complement, and triangular.

Design and Comparison of Wallace Multiplier Based on Symmetric Stacking and High Speed counters

High latency and efficient addition of multiple operands is an essential operation in any computational unit. The latency, power efficiency and area of multiplier circuits is of critical importance in the performance of processors. Multiplier circuits are an essential part of an arithmetic logic unit, or a digital signal processor system for performing filtering and convolution. The binary multiplication of integers or fixed-point numbers results in partial products that must be added to produce the final product. The addition of these partial products dominates the latency and power consumption of the multiplier. In order to combine the partial products efficiently, column compression is commonly used. Many methods have been presented to optimize the performance of the partial product summation previously. To achieve higher efficiency, more number of bits need to be reduced at a time. For this, the column compression techniques can be used. By using this, the critical path delay can be reduced and also the latency of the multiplier. When higher compression unit is used the energy of the multiplier is also reduced. In this paper, the column compression techniques are compared. The stacking circuits presented in, show an improvement over algorithmic Wallace multiplier which uses the generic equations for the column compression units. In stacking units, the 7:3 and 6:3 counters are derived from a basic 3-bit stacking circuit reducing usage of XOR gates. This reduces the usage of XOR gates and thus the critical delay. While the algorithmic units use generic equations using the generation and propagation functions of an adder.

Efficient FPGA-based FIR – architecture and its significance in ultrasonic signal processing

The presented work demonstrates the most suitable architecture for the FPGA-based signal processing which makes available various real-time filtering algorithms, such as band pass, high pass, low pass, and band-reject for FIR filters. The processor was implemented with the fixed-point arithmetic using VHDL, which can be downloadable on FPGA device. The FPGA device can be interfaced with an analog-to-digital converter (ADC), digital-to-analog converter (DAC) and a personal computer with MATLAB for the user interface and feeding coefficients and order of the filter. The core part of this paper was to find the reconfigurable and efficient architecture of the processor with only one multiplier which can work for Finite Impulse response (FIR) filter with the best- suited structure. The system will be used for automatic generation of fixed-point FIR filters. The model was also implemented in MATLAB script and the verification of results in the case of low-pass filtering confirmed that both models in MATLAB and VHDL matched to each other. All components of architecture in VHDL were designed using generics which allow changing its structure and behavior by generic values. Therefore, it is a universal filter platform where user can process the data while changing the filter parameters as per the requirement of applications. The complete design was verified by taking the example of audio signal frequency, but parameterized components of system architecture can also facilitate its applicability at ultrasonic frequencies by changing the algorithm. The significance and applicability of FPGAs in ultrasonic signal processing were also studied and reviewed.

Implementation of FPGA based MRPMA for high performance applications

In the last few decay, Network on Chip’s (NoC) are the powerful chips for high speed communications pertaining to 802.11 Ethernet protocol which is a need to be reconfigurable for successful data frame transmission. The existing architectures like coarse grained reconfigurable, ALU cluster and expression grain reconfigurable architecture and look-up-table used in fine grained reconfigurable devices requires a lot of storage memory, hardware resources such as slices, cell area and cell delay. To tackle these issues, Multigrained Reconfiguration and Parallel Mapping Architecture (MRPMA) is proposed and their performance analysis parameters are calculated. The MRPMA uses the four contributions to optimize Processing Elements (PE’s) operations: 1) Fast Fourier Transformation (FFT) to perform fixed point numbers to the configuration words, 2) Discrete Cosine Transformation (DCT) to analyze the data in the frequency domain, 3) Finite Impulse Response (FIR) for parallel mapping the data and 4) Channel encoder and decoder to encode the data and to calculate the shortest route from source to destination switch.

Efficient Reconfigurable Architecture for Pricing Exotic Options

This article presents a new method for Monte Carlo (MC) option pricing using field-programmable gate arrays (FPGAs), which use a discrete-space random walk over a binomial lattice, rather than the continuous space-walks used by existing approaches. The underlying hypothesis is that the discrete-space walk will significantly reduce the area needed for each MC engine, and the resulting increase in parallelisation and raw performance outweighs any accuracy losses introduced by the discretisation. Experimental results support this hypothesis, showing that for a given MC simulation size, there is no significant loss in accuracy by using a discrete space model for the path-dependent exotic financial options. Analysis of the binomial simulation model shows that only limited-precision fixed-point arithmetic is needed, and also shows that pairs of MC kernels are able to share RAM resources. When using realistic constraints on pricing problems, it was found that the size of a discrete-space MC engine can be kept to 370 Flip-Flops and 233 Lookup Tables, allowing up to 3,000 variance-reduced MC cores in one FPGA. The combination of a highly parallelisable architecture and model-specific optimisations means that the binomial pricing technique allows for a 50× improvement in throughput compared to existing FPGA approaches, without any reduction in accuracy.

A Fully-Pipelined Hardware Design for Gaussian Mixture Models

Gaussian Mixture Models (GMMs) are widely used in many applications such as data mining, signal processing and computer vision, for probability density modeling and soft clustering. However, the parameters of a GMM need to be estimated from data by, for example, the Expectation-Maximization algorithm for Gaussian Mixture Models (EM-GMM), which is computationally demanding. This paper presents a novel design for the EM-GMM algorithm targeting reconfigurable platforms, with five main contributions. First, a pipeline-friendly EM-GMM with diagonal covariance matrices that can easily be mapped to hardware architectures. Second, a function evaluation unit for Gaussian probability density based on fixed-point arithmetic. Third, our approach is extended to support a wide range of dimensions or/and components by fitting multiple pieces of smaller dimensions onto an FPGA chip. Fourth, we derive a cost and performance model that estimates logic resources. Fifth, our dataflow design targeting the Maxeler MPC-X2000 with a Stratix-5SGSD8 FPGA can run over 200 times faster than a 6-core Xeon E5645 processor, and over 39 times faster than a Pascal TITAN-X GPU. Our design provides a practical solution to applications for training and explores better parameters for GMMs with hundreds of millions of high dimensional input instances, for low-latency and high-performance applications.

A Resource-Limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications

In this brief, we introduce an architecture for accelerating convolution stages in convolutional neural networks (CNNs) implemented in embedded vision systems. The purpose of the architecture is to exploit the inherent parallelism in CNNs to reduce the required bandwidth, resource usage, and power consumption of highly computationally complex convolution operations as required by real-time embedded applications. We also implement the proposed architecture using fixed-point arithmetic on a ZC706 evaluation board that features a Xilinx Zynq-7000 system on-chip, where the embedded ARM processor with high clocking speed is used as the main controller to increase the flexibility and speed. The proposed architecture runs under a frequency of 150 MHz, which leads to 19.2 Giga multiply accumulation operations per second while consuming less than 10 W in power. This is done using only 391 DSP48 modules, which shows significant utilization improvement compared to the state-of-the-art architectures.

Stochastic degradation of the fixed-point version of 2D-chaotic maps

This paper deals with a family of interesting 2D-quadratic maps proposed by Sprott, in his seminal paper [1], related to “chaotic art”. Our main interest about these maps is their great potential for using them in digital electronic applications because they present multiple chaotic attractors depending on the selected point in the parameter’s space. Only results for the analytical representation of these maps have been published in the open literature. Consequently, the objective of this paper is to extend the analysis to the digital version, to make possible the hardware implementation in a digital medium, like field programmable gate arrays (FPGA) in fixed-point arithmetic. Our main contributions are: (a) the study of the domains of attraction in fixed-point arithmetic, in terms of period lengths and statistical properties; (b) the determination of the threshold of the bus width that preserves the integrity of the domain of attraction and (c) the comparison between two quantifiers based on respective probability distribution functions (PDFs) and the well known maximum Lyapunov exponent (MLE) to detect the above mentioned threshold.

Implementation of neuro-fuzzy system with modified high performance genetic algorithm on embedded systems

In this paper implementation of ANFIS on embedded systems based on single-core and multi-core ARM processors is presented. A novel evolutionary optimization tool named, modified high performance genetic algorithm (mHPGA) with bacterial conjugation operator is applied to ANFIS as a training method. Fixed point and floating point number representations are applied and compared. Moreover new mutation algorithm has been proposed for fixed point numbers. The proposed method is designed to sweep numbers space to search possible solutions in large state space. Concurrency nature of mHPGA benefits implementation of multi threading feature on ARM cortex-A53 with four cores.

Training Fixed-Point Classifiers for On-Chip Low-Power Implementation

In this article, we develop several novel algorithms to train classifiers that can be implemented on chip with low-power fixed-point arithmetic with extremely small word length. These algorithms are based on Linear Discriminant Analysis (LDA), Support Vector Machine (SVM), and Logistic Regression (LR), and are referred to as LDA-FP, SVM-FP, and LR-FP, respectively. They incorporate the nonidealities (i.e., rounding and overflow) associated with fixed-point arithmetic into the offline training process so that the resulting classifiers are robust to these nonidealities. Mathematically, LDA-FP, SVM-FP, and LR-FP are formulated as mixed integer programming problems that can be robustly solved by the branch-and-bound methods described in this article. Our numerical experiments demonstrate that LDA-FP, SVM-FP, and LR-FP substantially outperform the conventional approaches for the emerging biomedical applications of brain decoding.

Resource-Efficient Gradient Methods for Model Predictive Pulse Pattern Control on an FPGA

We demonstrate that an optimization-based model predictive pulse pattern controller can be designed with a complexity in terms of hardware resource usage on a field-programmable gate array (FPGA) that is comparable to that of a conventional controller. The keys to the superior performance and resource usage over existing solution methods for model predictive pulse pattern control are an appropriate problem reformulation and a newly derived result for the projection on the truncated monotone cone that composes the feasible set in this application. Using a coldstarted classic gradient method in fixed-point arithmetic, a numerically stable implementation is shown to require less than 300 clock cycles to meet the stringent accuracy specification for problems with at most three switching transitions per phase. For the case of four (five) transitions, only about 550 (690) cycles are required. At the same time, merely two digital signal processor (DSP)-type multipliers on an FPGA are used for all problem sizes. These results indicate a speed improvement of ten times and a resource reduction by 17 times in terms of DSP-type multipliers for the case of three transitions per phase compared with an existing solution method. When there are four or five transitions per phase, the resource reduction is even more impressive.

Real-Time and High-Accuracy Arctangent Computation Using CORDIC and Fast Magnitude Estimation

This paper presents an improved VLSI (Very Large Scale of Integration) architecture for real-time and high-accuracy computation of trigonometric functions with fixed-point arithmetic, particularly arctangent using CORDIC (Coordinate Rotation Digital Computer) and fast magnitude estimation. The standard CORDIC implementation suffers of a loss of accuracy when the magnitude of the input vector becomes small. Using a fast magnitude estimator before running the standard algorithm, a pre-processing magnification is implemented, shifting the input coordinates by a proper factor. The entire architecture does not use a multiplier, it uses only shift and add primitives as the original CORDIC, and it does not change the data path precision of the CORDIC core. A bit-true case study is presented showing a reduction of the maximum phase error from 414 LSB (angle error of 0.6355 rad) to 4 LSB (angle error of 0.0061 rad), with small overheads of complexity and speed. Implementation of the new architecture in 0.18 µm CMOS technology allows for real-time and low-power processing of CORDIC and arctangent, which are key functions in many embedded DSP systems. The proposed macrocell has been verified by integration in a system-on-chip, called SENSASIP (Sensor Application Specific Instruction-set Processor), for position sensor signal processing in automotive measurement applications.

Towards a Compiler for Reals

Numerical software, common in scientific computing or embedded systems, inevitably uses a finite-precision approximation of the real arithmetic in which most algorithms are designed. In many applications, the roundoff errors introduced by finite-precision arithmetic are not the only source of inaccuracy, and measurement and other input errors further increase the uncertainty of the computed results. Adequate tools are needed to help users select suitable data types and evaluate the provided accuracy, especially for safety-critical applications. We present a source-to-source compiler called Rosa that takes as input a real-valued program with error specifications and synthesizes code over an appropriate floating-point or fixed-point data type. The main challenge of such a compiler is a fully automated, sound, and yet accurate-enough numerical error estimation. We introduce a unified technique for bounding roundoff errors from floating-point and fixed-point arithmetic of various precisions. The technique can handle nonlinear arithmetic, determine closed-form symbolic invariants for unbounded loops, and quantify the effects of discontinuities on numerical errors. We evaluate Rosa on a number of benchmarks from scientific computing and embedded systems and, comparing it to the state of the art in automated error estimation, show that it presents an interesting tradeoff between accuracy and performance.

Faster, Stabler, and Simpler—A Recursive-Least-Squares Algorithm Exploiting the Frisch–Waugh–Lovell Theorem

We propose a novel recursive least squares (RLS) algorithm that exploits the Frisch–Waugh–Lovell theorem to reduce digital complexity and improve convergence speed and algorithmic stability in fixed-point arithmetic. We tested the new algorithm in the digital background calibration section of a four-channel time-interleaved analog-to-digital converter, obtaining better stability and faster convergence. The digital complexity of the new algorithm in terms of multiplications and divisions is 33% lower asymptotically than that of the conventional Bierman algorithm if the model parameters need not be computed at each update; otherwise, it is the same. Memory requirements are also the same. Because, in calibration, the distance between the ideal and calibrated outputs of the system is to be minimized, the actual value of the model parameters is usually not of interest. Convergence time can be up to 10 or 20 times better in fixed-point arithmetic, and stability for large models is also better in our simulations. In our simulations, when the conventional Bierman RLS algorithm is stable, the steady-state accuracy of the new algorithm is either comparable or better, depending on the simulation setup.

A Fast Estimation Method for the Phase Difference Between Two Quasi-harmonic Signals for Real-Time Systems

We propose a new method of phase difference estimation between two quasi-harmonic signals with slowly varying parameters. The proposed method does not require the solution of the overdetermined systems of equations, and it may be calculated in real time. The majority of operations for their calculation can be carried out on fixed-point numbers, and that substantially simplifies algorithm realization on signal processor or FPGA. The method accuracy is near to the Cramer---Rao lower bound within the statistical error for signals with SNR is in the range from 0 to 40 dB. The advantage of the proposed method is the possibility of signal processing with slow frequency and amplitude modulation. We compare proposed method and the method based on sine-wave-fits by numerical simulation.

Compressed fixed-point data formats with non-standard compression factors

Sign bit compression in fixed-point numbering systems can improve the dynamic range and round-off noise for signal processing algorithms. This paper analyses non-standard compression factors (CF) for compressed fixed-point data formats, where sign bit compression is performed on each individual fixed-point number. Although these compression techniques are applicable to other fixed-point formats, the compressed two's complement data format is selected for illustration. A brief background on compressed two's complement is provided. Obvious compression factors are powers of two due to binary formatting, but compression factors other than standard powers of two are presented. Compression factors of 3 and 5 are analysed in greater detail. Motivation for and advantages of non-power-of-two compression factors are identified.