Fixed-point Arithmetic Research Articles

A distance-based compression of 3D meshes for mobile devices

We present a new 3D mesh codec for mobile devices. Mobile devices have limited resources such as low memory, slow CPU speed, low power, and no floating-point processor. Considering these mobile characteristics, we suggest a new approach: a hybrid of a progressive geometry and a single-rate connectivity coding. By this approach, our algorithm achieves fast visual updates of progressive 3D point clouds on a small screen of a mobile device and later finalizes restoring faces of the mesh without intensive computing. For a progressive geometry coding, an octree is created and coded. For a single-rate connectivity coding, a new distance based algorithm is introduced. Our algorithm uses only fixed-point arithmetic with simple data structures. Our new 3D mesh codec has been tested on a real mobile phone and the statistical and visual results are also presented in this paper.

Array-Based QR-RLS Multichannel Lattice Filtering

An array-based algorithm for multichannel lattice filtering is proposed. The filter is formed by a set of units that are adapted locally and concurrently using recursions that closely match those for single-channel lattice filters. The design, based on a known modular decomposition approach, allows for unequal filter lengths to be specified for different input channels. Individual units are updated using a square-root recursive least-squares (RLS) algorithm in array form that relies mainly on Givens rotations and exhibits highly favorable numerical behavior and a regular structure that is appealing from a hardware implementation perspective. Iterative implementations of Givens rotations using the Newton method and cordic processors are examined in the context of fixed-point implementations. A procedure based on three cordic steps is proposed to handle complex data that arise in several applications of multichannel filtering. Algorithm initialization issues are also addressed. The array algorithm is compared in simulation with plain RLS, QR-RLS, and two related multichannel lattice algorithms. Its performance is shown to be comparable to that of other QR-decomposition-based algorithms under fixed-point arithmetic. In particular, it retains desirable graceful degradation properties as the numerical precision decreases.

Implementing plastic weights in neural networks using low precision arithmetic

In this letter, we develop a fixed-point arithmetic, low precision, implementation of an exponentially weighted moving average (EWMA) that is used in a neural network with plastic weights. We analyze the proposed design both analytically and experimentally, and we also evaluate its performance in the application of an attractor neural network. The EWMA in the proposed design has a constant relative truncation error, which is important for avoiding round-off errors in applications with slowly decaying processes, e.g. connectionist networks. We conclude that the proposed design offers greatly improved memory and computational efficiency compared to a naïve implementation of the EWMA's difference equation, and that it is well suited for implementation in digital hardware.

Rapid Prototyping of Activity Recognition Applications

The CRN Toolbox enables fast implementation of activity and context recognition systems, featuring mechanisms for distributed processing and support for mobile and wearable devices. CRN Toolbox is a tool set specifically optimized for implementing multimodal, distributed activity and context recognition systems running on Posix operating systems. Like conventional rapid- prototyping tools, the CRN Toolbox contains a collection of ready-to-use algorithms (signal processing, pattern classification, and so on). Unlike classic event detection in homogeneous sensor networks-for example, DSWare (Data Service Middleware)-it supports complex activity detection from heterogeneous sensors. Its implementation is particularly optimized for mobile devices. This includes the ability to execute algorithms, whether in floating-point or fixed-point arithmetic, without recoding. Moreover, with its mature functionality, the CRN Toolbox isn't likely to suffer from limited user acceptance as the Context toolkit framework did.

FPGA acceleration of a quantum Monte Carlo application

Quantum Monte Carlo methods enable us to determine the ground-state properties of atomic or molecular clusters. Here, we present a reconfigurable computing architecture using Field Programmable Gate Arrays (FPGAs) to accelerate two computationally intensive kernels of a Quantum Monte Carlo (QMC) application applied to N-body systems. We focus on two key kernels of the QMC application: acceleration of potential energy and wave function calculations. We compare the performance of our application on two reconfigurable platforms. Firstly, we use a dual-processor 2.4 GHz Intel Xeon augmented with two reconfigurable development boards consisting of Xilinx Virtex-II Pro FPGAs. Using this platform, we achieve a speedup of 3× over a software-only implementation. Following this, the chemistry application is ported to the Cray XD1 supercomputer equipped with Xilinx Virtex-II Pro and Virtex-4 FPGAs. The hardware-accelerated application on one node of the high performance system equipped with a single Virtex-4 FPGA yields a speedup of approximately 25× over the serial reference code running on one node of the dual-processor dual-core 2.2 GHz AMD Opteron. This speedup is mainly attributed to the use of pipelining, the use of fixed-point arithmetic for all calculations and the fine-grained parallelism using FPGAs. We can further enhance the performance by operating multiple instances of our design in parallel.

A Primer on Fractions

The decision to use fixed-point arithmetic on an integer CPU or floating-point on a specialized processor is one that is common not only in digital signal processing applications, but also in many embedded applications. It is a typical engineering tradeoff fixed-point processing is cheaper, being implementable on common integer hardware, but the algorithms are complicated and the capabilities are limited; floating-point processing requires specialized hardware with additional cost, but the ease of programming and the extra range may be critical to completing the task. Other factors such as computation speed, power, and algorithm development may also be factors to consider. Your specific application may dictate which of the two you select.

A support vector machine with integer parameters

We describe here a method for building a support vector machine (SVM) with integer parameters. Our method is based on a branch-and-bound procedure, derived from modern mixed integer quadratic programming solvers, and is useful for implementing the feed-forward phase of the SVM in fixed–point arithmetic. This allows the implementation of the SVM algorithm on resource–limited hardware like, for example, computing devices used for building sensor networks, where floating–point units are rarely available. The experimental results on well–known benchmarking data sets and a real–world people-detection application show the effectiveness of our approach.

High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4

There is increasing interest about floating-point arithmetics in field programmable gate arrays (FPGAs) because of the increase in their size and performance. FPGAs are generally good at bit manipulations and fixed-point arithmetics, but they have a harder time coping with floating-point arithmetics. An architecture used to construct high-performance floating-point components in a Virtex-4 FPGA is described in detail. Floating-point adder/subtracter and multiplier units have been constructed. The adder/subtracter can operate at a frequency of 377 MHz in a Virtex-4SX35 (speed grade -12).

Power and Area-Efficient Unified Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems

A unified computation method of vector and elementary functions is proposed for handheld 3D graphics systems. It unifies vector operations like vector multiply, multiply-and-add, divide, divide-by-square-root, and dot product and elementary functions like trigonometric, inverse trigonometric, hyperbolic, inverse hyperbolic, power (xy with two variables), and logarithm to an arbitrary base into a single four-way arithmetic platform. A number system called the fixed-point hybrid number system (FXP-HNS), which combines the fixed-point number system (FXP) and the logarithmic number system (LNS), is proposed for the power and area-efficient unification. Power and area-efficient logarithmic and antilogarithmic conversion schemes are also proposed for the data conversions between fixed-point and logarithmic numbers in the FXP-HNS and achieve 0.41 percent and 0.08 percent maximum conversion errors, respectively. The unified arithmetic unit based on the proposed schemes is presented with less than 6.3 percent operation error. Its fully pipelined architecture achieves single-cycle throughput with maximum four-cycle latency for all of the supported operations. Comparison results show that the proposed arithmetic unit achieves 30 percent power and 10.9 percent area reductions and runs two times faster than the previous approach.

Semantic inheritance in unifying theories of programming

Abstract This paper introduces a number of new techniques that support systematic manipulation of predicates, operators, healthiness conditions, laws and fixpoints of recursive programs. Necessary restrictions are imposed on the definition of each model so that the inheritance relation can be established by checking a few conditions on the healthiness conditions and the commands. In particular, we intend to identify the conditions that simplify the closure proof of the program operators and enable laws and fixpoints of a model to be inherited by its submodel without re-proof. A recursive program may correspond to different recursive functions in a model and its submodels, because the primitives such as abort and assignment statements are normally represented as different predicates in different models (although the original definition of each operator is unchanged). This paper studies meta-theory in this more general setting. A fixpoint theorem is discovered and applied to clarify the relationship between the partially correct relational model and the totally correct sequential model in UTP. It is shown that, although assignment statements are modified by the new healthiness conditions in the latter model, most laws (including many that are re-proved in UTP) and fixpoints can be inherited directly without re-proof, if the first argument of every sequential composition in each command tree corresponds to a terminating computation. This result also singles out a small number of laws and fixpoints that may no longer hold in the totally correct model.

Signed words and permutations, V; a sextuple distribution

We calculate the distribution of the sextuple statistic over the hyperoctahedral group B n that involves the flag-excedance and flag-descent numbers “fexc” and “fdes,” the flag-major index “fmaj,” the positive and negative fixed point numbers “ \(\mathop{\rm fix}\nolimits ^{+}\) ” and “ \(\mathop{\rm fix}\nolimits ^{-}\) ” and the negative letter number “neg.” Several specializations are considered. In particular, the joint distribution for the pair \((\mathop{\rm fexc}\nolimits ,\mathop{\rm fdes}\nolimits )\) is explicitly derived.

An optimization method focusing on fixed‐point arithmetic in applications for dynamically reconfigurable processor

AbstractDynamically reconfigurable processors such as the Dynamically Reconfigurable Processor (DRP) released by NEC Electronics are composed of many interconnected coarse‐grained arithmetic blocks. Applications for DRP are described in a programming language like C and parallelism in the source code is automatically extracted by a compiler. At the same time, it is also important to optimize descriptions so that the potential performance of the device is effectively brought out. In this paper, we propose an optimized coding method to improve efficiency of parallel processing on DRP. In this technique, the same kind of multicycle operations are aggregated into single functions, keeping the sequential framework of a programming language. The effects of the method are evaluated with ray tracing processing as an example application. As a result, the proposed technique achieves 2.68 to 3.09 times performance improvement without large increase in the number of states nor severe degradation of the frequency. © 2007 Wiley Periodicals, Inc. Syst Comp Jpn, 38(14): 20–28, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.20780

Implementing Spiking Neural Networks for Real-Time Signal-Processing and Control Applications: A Model-Validated FPGA Approach

In this paper, we present two versions of a hardware processing architecture for modeling large networks of leaky-integrate-and-fire (LIF) neurons; the second version provides performance enhancing features relative to the first. Both versions of the architecture use fixed-point arithmetic and have been implemented using a single field-programmable gate array (FPGA). They have successfully simulated networks of over 1000 neurons configured using biologically plausible models of mammalian neural systems. The neuroprocessor has been designed to be employed primarily for use on mobile robotic vehicles, allowing bio-inspired neural processing models to be integrated directly into real-world control environments. When a neuroprocessor has been designed to act as part of the closed-loop system of a feedback controller, it is imperative to maintain strict real-time performance at all times, in order to maintain integrity of the control system. This resulted in the reevaluation of some of the architectural features of existing hardware for biologically plausible neural networks (NNs). In addition, we describe a development system for rapidly porting an underlying model (based on floating-point arithmetic) to the fixed-point representation of the FPGA-based neuroprocessor, thereby allowing validation of the hardware architecture. The developmental system environment facilitates the cooperation of computational neuroscientists and engineers working on embodied (robotic) systems with neural controllers, as demonstrated by our own experience on the Whiskerbot project, in which we developed models of the rodent whisker sensory system.

Systolic FFT Processors: A Personal Perspective

This paper provides a personal perspective on developments in the implementation of two systolic fast Fourier transform processors over the last 25 years and identifies some of the lessons learned. This has been a period of tremendous advancements in integrated circuit technology that is demonstrated by the resulting processors. The first processor is the Modular Transform Processor that was developed at TRW in the 1982---1984 time frame using VLSI technology. It is a set of six large circuit boards that computes 4,096-point fast Fourier transforms using 22-bit floating-point arithmetic at sustained data rates of 40 MSPS. The second processor is a single ASIC chip systolic FFT processor developed by the Mayo Foundation in the 2001---2002 time frame that computes 4,096-point FFTs using 16-bit fixed-point arithmetic at sustained data rates of 200 MSPS. Some thoughts on the future directions of systolic FFT processor development are offered. Future systems will compute large transforms (e.g., 16 K-point to 1 M-point) at high data rates (e.g., 500 MSPS to 1 GSPS), will employ more precise arithmetic (e.g., 32-bit single precision IEEE Standard floating-point arithmetic), will consume very low power (e.g., on the order of one watt) and will be realized on a single chip.

Implementation of Fixed-Point Control Algorithms Based on the Modified Delta Operator and Form for Intelligent Systems

The methodology we propose for realizing energy- and space-saving adaptive control algorithms is based on pulse width modulation (PWM) with a modified delta operator. The dynamic calculation range is at least twice that of the conventional range, making it very useful in embedded real-time intelligent and micromechatronic systems because complex control algorithms can be implemented in fixed-point arithmetic with short words. Simulation results for PID control and simple adaptive control demonstrate the practicality and effectiveness of our proposal.

Analysis of quantization effects on high-order function neural networks

In this paper we investigate the combined effects of quantization and clipping on high-order function neural networks (HOFNN). Statistical models are used to analyze the effects of quantization in a digital implementation. We analyze the performance degradation caused as a function of the number of fixed-point and floating-point quantization bits under the assumption of different probability distributions for the quantized variables, and then compare the training performance between situations with and without weight clipping. We establish and analyze the relationships for a true nonlinear neuron between inputs and outputs bit resolution, training and quantization methods, network order and performance degradation, all based on statistical models, and for on-chip and off-chip training. Our experimental simulation results verify the presented theoretical analysis.

FPGA implementation of a systems identification module based upon Hopfield networks

The aim of this contribution is to implement a hardware module that performs parametric identification of dynamical systems. The design is based upon the methodology of optimization with Hopfield neural networks, leading to an adapted version of these networks. An outstanding feature of this modified Hopfield network is the existence of weights that vary with time. Since weights can no longer be stored in read-only memories, these dynamic weights constitute a significant challenge for digital circuits, in addition to the usual issues of area occupation, fixed-point arithmetic and nonlinear functions computations. The implementation, which is accomplished on FPGA circuits, achieves modularity and flexibility, due to the usage of parametric VHDL to describe the network. In contrast to software simulations, the natural parallelism of neural networks is preserved, at a limited cost in terms of circuitry cost and processing time. The functional simulation and the synthesis show the viability of the design. In particular, the FPGA implementation exhibits a reasonably fast convergence, which is required to produce accurate parameter estimations. Current research is oriented towards integrating the estimator within an embedded adaptive controller for autonomous systems.

The Negative Two’s Complement Number System

The two's complement fractional fixed-point number system is widely used to implement digital signal processing on VLSI chips. It has a range of values from ?1 to one least significant bit below +1. Either the multiplication of ?1 ? ?1 or taking the absolute value of ?1 produces a result (+1) that cannot be represented. A new system, the negative two's complement number system, is described here that has a range of one least significant bit above ?1 to +1 which eliminates the problem. This paper presents the new number system and describes algorithms for the basic arithmetic operations.

Error analysis of digital filters using HOL theorem proving

When a digital filter is realized with floating-point or fixed-point arithmetics, errors and constraints due to finite word length are unavoidable. In this paper, we show how these errors can be mechanically analysed using the HOL theorem prover. We first model the ideal real filter specification and the corresponding floating-point and fixed-point implementations as predicates in higher-order logic. We use valuation functions to find the real values of the floating-point and fixed-point filter outputs and define the error as the difference between these values and the corresponding output of the ideal real specification. Fundamental analysis lemmas have been established to derive expressions for the accumulation of roundoff error in parametric Lth-order digital filters, for each of the three canonical forms of realization: direct, parallel, and cascade. The HOL formalization and proofs are found to be in a good agreement with existing theoretical paper-and-pencil counterparts.

An optimal structure for implementation of digital filters

In this paper, different structures for an elliptic filter with fixed-point arithmetic are implemented and compared. The filter must be quantized for hardware implementation. This quantization is done in two steps. First the coefficients of the filter are quantized and then the minimum required accuracy of the internal nodes is determined. According to the simulation results, lattice and DFII-parallel structures have minimal sensitivity to coefficient quantization. Also, the chip areas (i.e. gate counts)of different structures are computed. We show that overall, the DFI-parallel structure is the optimal structure for hardware implementation and requires minimal chip area at the needed precision.