The Negative Two’s Complement Number System

Abstract

The two's complement fractional fixed-point number system is widely used to implement digital signal processing on VLSI chips. It has a range of values from ?1 to one least significant bit below +1. Either the multiplication of ?1 ? ?1 or taking the absolute value of ?1 produces a result (+1) that cannot be represented. A new system, the negative two's complement number system, is described here that has a range of one least significant bit above ?1 to +1 which eliminates the problem. This paper presents the new number system and describes algorithms for the basic arithmetic operations.