Abstract
AbstractDynamically reconfigurable processors such as the Dynamically Reconfigurable Processor (DRP) released by NEC Electronics are composed of many interconnected coarse‐grained arithmetic blocks. Applications for DRP are described in a programming language like C and parallelism in the source code is automatically extracted by a compiler. At the same time, it is also important to optimize descriptions so that the potential performance of the device is effectively brought out. In this paper, we propose an optimized coding method to improve efficiency of parallel processing on DRP. In this technique, the same kind of multicycle operations are aggregated into single functions, keeping the sequential framework of a programming language. The effects of the method are evaluated with ray tracing processing as an example application. As a result, the proposed technique achieves 2.68 to 3.09 times performance improvement without large increase in the number of states nor severe degradation of the frequency. © 2007 Wiley Periodicals, Inc. Syst Comp Jpn, 38(14): 20–28, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.20780
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