FinFET Static Random Access Memory Research Articles

Gate breakdown induced stuck bits in sub-20 nm FinFET SRAM

This paper discusses the stuck bits induced by the gate breakdown of PMOS in the sub-20 nm FinFET static random access memory (SRAM) device. After the heavy-ion experiment, several stuck bits are in the FinFET SRAM matrix, which cannot be set or reset. To investigate the factors that caused the stuck bit, we perform the electrical failure analysis (EFA) to measure the electric characteristics of the transistors in the stuck bits and normal cells separately. The measurement results show a clear gate breakdown at the PMOS pull-up (PPU) transistor in all of the measured SRAM cells. Meanwhile, the SPICE simulation based on the EFA results verifies the impact of the damaged PPU. Finally, considering all of the phenomena, the charge deposition from single events is the major mechanism that causes the stuck bits in FinFET SRAM. The experiment results alert a potential gate breakdown risk in the ultra-high-density FinFET SRAM applied in the space environment.

A novel high-performance TG-based SRAM cell with 5 nm FinFET technology

In this study, we investigate the performance and reliability of a novel static random-access memory (SRAM) cell utilizing advanced 5 nm FinFET technology. Our research aims to address critical challenges in SRAM design by integrating transmission gates and power gated transistors. Through extensive simulations using the Cadence Virtuoso tool, we optimize the SRAM cell’s read and write paths, resulting in substantial improvements in both functionalities. Additionally, our study unveils temperature-dependent variations in the read current and write margin, emphasizing the influence of temperature on SRAM performance. Compared to conventional FinFET SRAM circuits of equivalent bit-cell area and read latency, our innovative design showcases remarkable improvements across various parameters. Specifically, we achieve a commendable increase of 6.16% in the write static noise margin (WSNM) and 5.86% in the hold static noise margin (HSNM). Moreover, our findings reveal a substantial boost in read stability, increasing from 14.75% to 18.35%. These advancements underscore the promising potential of our approach in paving the way for future innovations in high-performance memory architectures. By leveraging state-of-the-art technology and meticulous optimization techniques, our research sets a new standard for SRAM design, offering enhanced performance, reliability, and efficiency in memory systems.

Ultra-Low Power 9T FinFET Based SRAM Cell for IoT Applications

The rapid proliferation of Internet of Things (IoT) devices has escalated the demand for energy-efficient memory solutions. The development of SRAM (Static Random-Access Memory) has gathered significant attention, particularly for low-power applications and portable devices. This research introduces a novel approach to ensure robust performance and operational integrity, all while adhering to stringent power constraints amidst process and temperature fluctuations. This quest for alternative nano-devices has been ignited by the scaling and channel control challenges intrinsic to CMOS technology. Among the array of alternatives, including FinFETs, TFETs, and CNTFETs, FinFETs have emerged as strong contenders. FinFET SRAMs contribute to the ongoing drive for electronic devices to become more compact and energy-efficient. They offer a distinct advantage as a promising CMOS substitute, attributed to their high performance, stability, with low power consumption characteristics at the nanoscale. The study proposes an ultra-low power 9T FinFET based SRAM cell meticulously designed for IoT applications. Leveraging the unique attributes of FinFET based 9T cell, the proposed SRAM cell is tailored to achieving minimal power consumption while maintaining inherent stability. The study assesses the performance of the proposed SRAM cells for power dissipation, stability, speed, and energy efficiency, and compares them with existing SRAM structures. The results are obtained through the Monte Carlo simulation technique, which evaluates circuit performance under specified conditions. The study achieves remarkable efficiency gains with 9T SRAM cells compared to other configurations. Additionally, the reduced read and write access times facilitate expedited data retrieval and storage operations.

Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology

Many scientists are working to develop a static random-access memory (SRAM) cell that used little power and has good stability and speed. This work introduces a fin field effect transistor developed SRAM cell with 10 transistors (10T FinFET SRAM). A cross connected standard inverter and schmitt-trigger inverter is used in the proposed 10T FinFET SRAM cell. We introduce the schmitt trigger based SRAM cell with single-ended read decoupled and feedback-cutting approaches to enhance the static noise margin (SNM) and access time of the SRAM cell. The proposed cell’s power utilization is decreased with the help of stacked N-FinFETs. For determining the relative performance of the proposed 10T FinFET SRAM cell design in terms of fundamental design metrics, it has also been compared with some of the current SRAM cells, including 6T, SBL9T SRAM, 10T SRAM, and DS10T SRAM. The simulation results at 0.6V demonstrate that the suggested design achieves low power utilization when Reading, writing and hold modes of operation in comparison to the aforementioned bit cells. It maintains a high SNM during all operations. The suggested cell is the one with fastest read access. The simulation is carried out with cadence tool using FinFET 18 nm technology.

Reliable and low power Negative Capacitance Junctionless FinFET based 6T SRAM cell

The increasing demand of portable gadgets for emerging VLSI applications call for the low power 6 T static random-access memory (SRAM) cell design. In this work, a 6 T SRAM cell has been designed using Negative Capacitance Junctionless FinFET (NC-JL FinFET) device. Further, the NC-JL FinFET based 6 T SRAM cell is evaluated for its power, stability and delay performance for read, write, and hold states and compared with conventional JL FinFET and published JL FinFET based SRAM. To investigate the reliability, the impact of ferroelectric thickness (TFE) and supply voltage (VDD) on the performance of NC-JL FinFET SRAM has also been investigated. It is shown that NC-JL FinFET SRAM dissipates 20% and ∼33% less static and dynamic power, with 1.2-, 1.5- and 1.18-times enhanced static noise margins in read, write, and hold state, respectively than JL FinFET SRAM. It also provides 37% and 20% faster read and write operations.

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part I: CNFET Transistor Optimization

In this article, we propose a carbon nanotube (CNT) field-effect transistor (CNFET)-based static random access memory (SRAM) design at the 5-nm technology node that is optimized based on the tradeoff between performance, stability, and power efficiency. In addition to size optimization, physical model parameters including CNT density, CNT diameter, and CNFET flat band voltage are evaluated and optimized for CNFET SRAM performance improvement. Optimized CNFET SRAM is compared with state-of-the-art 7-nm FinFET SRAM cell based on Arizona State University [ASAP 7-nm FinFET predictive technology models (PTM)] library. We find that the read, write EDPs, and static power of the proposed CNFET SRAM cell are improved by 67.6%, 71.5%, and 43.6%, respectively, compared with the FinFET SRAM cell, with slightly better stability. CNT interconnects both inside and in-between CNFET SRAM cells are considered to compose an all-carbon-based SRAM (ACS) array which will be discussed in the Part II of this article. A 7-nm FinFET SRAM cell with copper interconnects is implemented and used for comparison.

Design and simulation of high-speed and low-power memcapacitor-based nonvolatile static cells using FinFET transistors

Metal–oxide–semiconductor field-effect transistors (MOSFETs) are mostly used in the design of static cells. MOSFETs have disadvantages, such as increased leakage current, reduced reliability, increased short-channel effects, and large changes in parameters. In this paper, fin field-effect transistors (FinFETs) are used instead of MOSFETs. Memristive elements are used in the design of a nonvolatile static cell. The memory cell presented here includes a static random access memory (SRAM) core (a 6T FinFET cell in this case) with two memristors and two memcapacitors, thus making a 6T FinFET SRAM cell-based 2R2C. The designed nonvolatile memory cell performed better in terms of power consumption, energy, areal factors, static noise margin, write margin, and read/write propagation delay than other designs presented so far. The figures of merit of the proposed design are also substantially improved, making the presented scheme a better approach for ‘read-write’ operations. In this paper, we have tried to keep the load capacitance ( as small as possible to improve the power consumption and the write and read delays, because the capacitor charge has a direct relationship with the cell’s power consumption.

Radiation Hardness Study of L G = 20 nm FinFET and Nanowire SRAM Through TCAD Simulation

Radiation hardness of FinFET and stacked nanowire (NW) static random-access memory (SRAM), with ${L} _{\text {G}} =20$ nm, which corresponds to high-density 5 nm technology node, is studied and compared using 3-D technology computer-aided design (TCAD) full cell domain simulation. Single FinFET and NW of similar total height are created using process simulation. Two types of NWs are studied, namely, high-performance and low-power NW, which has the same OFF-state and ON-state current as the FinFET, respectively. Device simulations are performed using transport parameters calibrated in Monte Carlo simulations. Radiation hardness of both n-type and p-type devices are simulated by striking particles at various locations and directions when the transistors are at OFF-state. It is found that NW is more robust than FinFET in all strike locations and directions. Radiation strikes are then applied to the OFF-state transistors in the SRAM at the most vulnerable positions. The SRAMs of both devices are designed to have similar noise margins for a fair comparison. It is found that NW SRAM is much more robust and can sustain two to three times higher linear energy transfer (LET) than FinFET SRAM in the most striking locations. Therefore, from a radiation robustness perspective, NW SRAM is preferred.

Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design

The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects. Graphene nanoribbon field-effect transistor (GNRFET) is an emerging technology that can potentially solve the issues of the conventional planar MOSFET imposed by quantum mechanical (QM) effects. GNRFET can also be used as static random-access memory (SRAM) circuit design due to its remarkable electronic properties. For high-speed operation, SRAM cells are more reliable and faster to be effectively utilized as memory cache. The transistor sizing constraint affects conventional 6T SRAM in a trade-off in access and write stability. This paper investigates on the stability performance in retention, access, and write mode of 15 nm GNRFET-based 6T and 8T SRAM cells with that of 16 nm FinFET and 16 nm MOSFET. The design and simulation of the SRAM model are simulated in synopsys HSPICE. GNRFET, FinFET, and MOSFET 8T SRAM cells give better performance in static noise margin (SNM) and power consumption than 6T SRAM cells. The simulation results reveal that the GNRFET, FinFET, and MOSFET-based 8T SRAM cells improved access static noise margin considerably by 58.1%, 28%, and 20.5%, respectively, as well as average power consumption significantly by 97.27%, 99.05%, and 83.3%, respectively, to the GNRFET, FinFET, and MOSFET-based 6T SRAM design.

SEE Sensitivity Evaluation for Commercial 16 nm SRAM-FPGA

Radiation effects can induce severe and diverse soft errors in digital circuits and systems. A Xilinx commercial 16 nm FinFET static random-access memory (SRAM)-based field-programmable gate array (FPGA) was selected to evaluate the radiation sensitivity and promote the space application of FinFET ultra large-scale integrated circuits (ULSI). Picosecond pulsed laser and high energy heavy ions were employed for irradiation. Before the tests, SRAM-based configure RAMs (CRAMs) were initialized and configured. The 100% embedded block RAMs (BRAMs) were utilized based on the Vivado implementation of the compiled hardware description language. No hard error was observed in both the laser and heavy-ion test. The thresholds for laser-induced single event upset (SEU) were ~3.5 nJ, and the SEU cross-sections were correlated positively to the laser’s energy. Multi-bit upsets were measured in heavy-ion and high-energy laser irradiation. Moreover, latch-up and functional interrupt phenomena were common, especially in the heavy-ion tests. The single event effect results for the 16 nm FinFET process were significant, and some radiation tolerance strategies were required in a radiation environment.

Implementation of High speed and Low power 6T SRAM cell using FinFET at 22nm technology

Static Random Access Memory (SRAM) comprises considerable proportion of total area and total power for almost all VLSI chips as cache memory for the System on Chip (SOC) and it is considered to be more intense in upcoming time in both handy devices and high-performance processors. Static Random Access Memory (SRAM) plays a most significant role in the microprocessor world, but as the technology is scaled down in nanometers, leakage current, leakage power and delay are the most common problems for SRAM cell which is basically designed in low power application. By using low-power FinFET based SRAM cell, we can accomplish higher steadfastness and enhanced battery life for handy devices. Our objective of this work is to improve delay and power consumption in proposed nanoscale 6T FinFET SRAM cell structure. The total leakage of FinFET SRAM cell is reduced by 23% after applying self controllable voltage level technique. The power consumption and write delay as well as read delay of proposed 6T FinFET based SRAM cell structure improves on CADENCE VIRTUOSO tool at 22nm technology scale.

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

Memory arrays consisting of Static Random Access Memory (SRAM) cells occupy the largest area on chip and are responsible for significant leakage power consumption in modern microprocessors. With the transition from planar Complementary Metal-Oxide-Semiconductor (CMOS) technology to FinFETs, FinFET SRAM design has become important. However, increasing leakage power consumption of FinFETs due to aggressive scaling, width quantization, read-write conflict, and process variations make FinFET SRAM design challenging. In this article, we show how Multiparameter Asymmetric (MPA) FinFETs can be used to design ultra-low-leakage and robust 6T SRAM cells. We combine multiple asymmetries, namely, asymmetry in gate work function, source/drain doping concentration, and gate underlap, to address various SRAM design issues all at once. We propose five novel MPA FinFET SRAM cell designs and compare them with symmetric and Single-Parameter Asymmetric (SPA) FinFET SRAM cells using dc and transient metrics. We show that the leakage current of MPA FinFET SRAM cells can be reduced by up to 58 × while ensuring reasonable read/write stability metric values. In addition, high stability metric values can be achieved with 22 × leakage current reduction compared to the traditional symmetric FinFET SRAM cell. There is no area overhead associated with MPA FinFET SRAM cells.

A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM

The impact of device variability, temperature, and technology CAD-based layout parasitics on low-voltage static random access memory (SRAM) yield is explored using a novel variability-aware statistical methodology. Threshold voltage, $V_{t}$ , mismatches for planar 22- and 14-nm FinFET SRAM transistors are characterized based on unique array-like structures for capturing process voltage and temperature (PVT) impact on variability. In general, the mismatches are shown to be a consistent and unique function of $V_{\rm dd}$ , doping, and temperature across the two technologies. Stronger $V_{t}$ mismatch impact is observed as a function of $V_{\rm dd}$ and doping in the 22-nm technology, with higher mismatch recorded at lower temperatures. In the 14-nm technology, doping is found to have the strongest impact on $V_{t}$ mismatch, and the mismatch increases with $V_{\rm dd}$ despite the reduced drain-induced barrier lowering effects. Similar to the 22-nm technology, the mismatch increases at lower temperatures. Front-end-of-the-line capacitance effects are found to be more significant than back-end-of-the-line effects in 14-nm technologies, as opposed to planar technologies. Accurate parasitic capacitance modeling along with PVT-aware variability process variations for different 22-/14-nm cell arrangements are incorporated into a physics-based statistical analysis methodology for accurate $V_{\rm min}$ analysis. The yield analysis results are corroborated with hardware yield using 4–16-Mb inline SRAM macro monitors. The methodology is unique in the industry, gives insight into the technology-circuit interactions, and is able to effectively predict the SRAM yield bounds.

Multi-Cell Soft Errors at Advanced Technology Nodes

For advanced technology nodes, the close proximity of semiconductor regions results in multiple regions collecting charge after an ion strike. This is especially true for static random access memory (SRAM) integrated circuits (ICs) where transistors are placed closer to each other compared to application-specific ICs (ASICs). As a result, SRAM ICs are highly vulnerable to multi-cell upsets (MCU). In this work, heavy-ion irradiations of bulk 28-nm planar and 16-nm FinFET SRAM ICs are investigated to show that small cell size for 16-nm node results in dominance of MCUs over single-cell upsets. Three-dimensional TCAD simulations showing the spread of well-potential perturbation as a function of particle LET support the experimental data. The size of the MCU cluster is also presented to determine the design parameters for error correcting codes (ECC) and interleaving for SRAM designs to meet performance requirements.

Analysis of Leakage Reduction Techniques in Independent-Gate DG FinFET SRAM Cell

Scaling of devices in bulk CMOS technology leads to short-channel effects and increase in leakage. Static random access memory (SRAM) is expected to occupy 90% of the area of SoC. Since leakage becomes the major factor in SRAM cell, it is implemented using FinFET. Further, double-gate FinFET devices became a better choice for deep submicron technologies. With this consideration in our research work, 6T SRAM cell is implemented using independent-gate DG FinFET in which both the opposite sides of gates are controlled independently which provides better scalability to the SRAM cell. The device is implemented using different leakage reduction techniques such as gated-Vdd technique and multithreshold voltage technique to reduce leakage. Therefore, power consumption in the SRAM cell is reduced and provides better performance. Independent-gate FinFET SRAM cell using various leakage reduction techniques has been simulated using Cadence virtuoso tool in 45 nm technology.

Strained SOI FINFET SRAM Design

Impact of strained silicon effects in double-gated FinFET structures on static random access memory (SRAM) cell functionality is presented. Three FinFET silicon-on-insulator (SOI) SRAM cell embodiments representing unstrained, strained, and NFET-only-strained devices are compared against a planar PDSOI SRAM cell design. The metrics encompass both static and dynamic behavior of the cell and are analyzed through 2-D process hardware-calibrated device models (Lg=25 nm). The key findings of this letter are: 1) PFET devices with tensile strain are found to degrade the FinFET cell Read Noise Margin and cell ability to write a strong “1”; 2) by restricting the tensile strain to the NFET devices FinFET SRAM cell Read stability and access times improve by 10%-20% relative to their unstrained FinFET and NFET-only strained PDSOI counterparts.

Device and Circuit Performance Estimation of Junctionless Bulk FinFETs

The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (Vth) roll-off characteristics at supply voltage (VDD) 1 V. Analyses of electron density and electricfield distributions in on-state and off-state also show that the JL devices have better on-off current ratios. Regarding design aspects, the effects of channel doping concentration (Nch) and Fin height (H)/width (W) on device Vth are also compared. In addition, the Vth of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (Nsub). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (tHL) and low-to-high delay time (tLH) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application.

Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights

We present the optimization of multiple-fin-height FinFET static random access memory (SRAM) to reduce cell leakage and improve the stability and density of SRAM. Using a taller fin FinFET for the pull-down device increases the read static noise margin of the SRAM and can potentially reduce the SRAM cell area. A reasonable amount of channel doping in all the transistors can be used to reduce the cell leakage current without appreciably degrading the stability of the SRAM cell. Increasing the channel doping of the access transistor simultaneously improves the read stability and decreases the cell leakage current of the SRAM cell.

Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits

This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$S.S.$</tex></formula> ) and comparable trap-induced <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{T}$</tex></formula> shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(V_{\rm dd})$</tex></formula> , the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way nand, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\sim$</tex></formula> 24%–27% and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\sim$</tex></formula> 13%–15% variations in leakage and delay at <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{ \rm dd} = \hbox{0.4}\ \hbox{V}$</tex></formula> , respectively, for the logic circuits evaluated.

Comparative Analysis of SEU in FinFET SRAM Cells for Superthreshold and Subthreshold Supply Voltage Operation

Subthreshold circuits are extensively used to reduce power consumption. However, increased susceptibility to radiation particles strikes can significantly impact the reliability of such systems. In this brief, we analyze different FinFET static-random-access-memory (SRAM) cells for single-event-upset immunity and compare their performance when operated with superthreshold and subthreshold supply voltage. Based on these observations, we propose several guidelines for radiation hardening of subthreshold FinFET SRAM designs. These guidelines suggest that the traditional radiation-hardening approaches need to be revisited for subthreshold designs.