Device and Circuit Performance Estimation of Junctionless Bulk FinFETs

Abstract

The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (Vth) roll-off characteristics at supply voltage (VDD) 1 V. Analyses of electron density and electricfield distributions in on-state and off-state also show that the JL devices have better on-off current ratios. Regarding design aspects, the effects of channel doping concentration (Nch) and Fin height (H)/width (W) on device Vth are also compared. In addition, the Vth of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (Nsub). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (tHL) and low-to-high delay time (tLH) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application.