Multi-Cell Soft Errors at Advanced Technology Nodes

Abstract

For advanced technology nodes, the close proximity of semiconductor regions results in multiple regions collecting charge after an ion strike. This is especially true for static random access memory (SRAM) integrated circuits (ICs) where transistors are placed closer to each other compared to application-specific ICs (ASICs). As a result, SRAM ICs are highly vulnerable to multi-cell upsets (MCU). In this work, heavy-ion irradiations of bulk 28-nm planar and 16-nm FinFET SRAM ICs are investigated to show that small cell size for 16-nm node results in dominance of MCUs over single-cell upsets. Three-dimensional TCAD simulations showing the spread of well-potential perturbation as a function of particle LET support the experimental data. The size of the MCU cluster is also presented to determine the design parameters for error correcting codes (ECC) and interleaving for SRAM designs to meet performance requirements.