Abstract
A large amount of data needs to be stored in integrated circuits when data are being processed. The integrated circuits contain a large amount of static random access memory (SRAM) due to its high level of integration and speed. SRAM units should be as small as possible to achieve higher storage density. In this work, the features of single cell upsets (SCUs) and multiple cell upsets (MCUs) in a full custom SRAM are tested for a 40 nm bulk CMOS technology node, and Ge (linear energy transfer (LET) = 37.3 MeV cm2/mg), Cl (LET = 13.1 MeV cm2/mg), Al (LET = 8.6 MeV cm2/mg), O (LET = 3.1 MeV cm2/mg), and Li (LET = 0.5 MeV cm2/mg) particles are used. The test results show that the total single cell upset events are 2,000,147, 1,124,269, 413,100, 311,311, and 47,815 under the irradiation of Ge, Cl, Al, O, and Li, respectively. Moreover, due to single event upset reversal mechanism, multiple cell upsets significantly decrease. The total multiple cell upset events are 10, 4, 0, 0, and 0 under the irradiation of Ge, Cl, Al, O, and Li, respectively. There are a lot of single cell upsets appearing under Ge, Cl, Al, O, and Li exposure. The number is increasing with increasing LET, which means that well contacts still need optimization in the full custom SRAM. Close spacing of well contacts or increasing contacts are the approaches used to drain the excess carriers quickly, and error detection and correction (EDAC) is used for SRAM technology. The features show that SCUs have become a major source of soft errors for the full custom SRAM. Combining close spacing of well contacts with error detection and correction (EDAC) and a well engineering scheme are used to reduce single cell upsets, although there are a few MCUs which are inevitable. Radiation hardened by design schemes needs to be further improved.
Highlights
With the development of technology, the design for high performance microprocessors has become more complex, among which the storage system, accounting for 70% of the total area of the microprocessor, is the core part of the microprocessor
The feature of single cell upset in the full custom static random access memory (SRAM) was carried out for a 40 nm bulk complementary metal oxide semiconductor (CMOS) technology
This indicates that single event cell upsets have become a major part of soft errors for the custom SRAM
Summary
With the development of technology, the design for high performance microprocessors has become more complex, among which the storage system, accounting for 70% of the total area of the microprocessor, is the core part of the microprocessor. This work investigates the effect of layout and well engineering on the single event error rate of SRAM on a 40 nm technology node. SERs(single event upset error rates) for SRAM are affected by the combination of structural layout, sensitive area per bit, and well engineering. At the 40 nm technology node, to take advantage of the single event upset reversal (SEUR) caused by scaling trends, the transistors are separated by a certain distance according to the design rules to reduce multiple cell upsets. The features of SCUs in a custom SRAM in 40 nm CMOS technology are widely reported, the effect of the structural layout and single event upset reversal on SCUs is rarely tested [14]. Features of single event error rate were widely tested by five heavy particles with different characteristics [18,19,20,21,22]
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