Field Programmable Gate Array Device Research Articles

Modeling and Designing of an All-Digital Resonate-and-Fire Neuron Circuit

Integrate-and-fire (IAF) and leaky integrate-and-fire (LIF) models are the popular models for spiking neurons and spiking neuron networks (SNN). They lack the dynamic properties of the ordinary differential equations (ODEs) model but are simpler. More than half of all neuron implementations were digital circuits. The majority of them were IAF and LIF models. The resonate-and-fire (RAF) model proposed by Izhikevich has both simplicity and dynamic properties. However, the RAF model does not have general structures for hardware implementation. Most realizations of the RAF neuron models were analog designs. In this study, we developed and simulated the model’s equations with digital pulses. Based on this analysis, we proposed block models of digital and all-digital RAF neurons to turn the models into digital hardware. We verified the properties of the proposed models by implementing an all-digital RAF neuron on a Intel 28 nm Cyclone V Field-programmable gate array (FPGA) device. The register-transfer level (RTL) structure of the implementation consumed fewer resources, with just 23 D flip-flops, without floating-point operations or multipliers.

A Coprocessor Architecture for 80/112-bit Security Related Applications

We have proposed a flexible coprocessor key-authentication architecture for 80/112-bit security-related applications over field by employing Elliptic-curve Diffie Hellman (ECDH) protocol. Towards flexibility, a serial input/output interface is used to load/produce secret, public, and shared keys sequentially. Moreover, to reduce the hardware resources and to achieve a reasonable time for cryptographic computations, we have proposed a finite field digit-serial multiplier architecture using combined shift and accumulate techniques. Furthermore, two finite-state-machine controllers are used to perform efficient control functionalities. The proposed coprocessor architecture over and is programmed using Verilog and then implemented on Xilinx Virtex-7 FPGA (field-programmable-gate-array) device. For and , the proposed flexible coprocessor use 1351 and 1789 slices, the achieved clock frequency is 250 and 235 MHz, time for one public key computation is 40.50 and 79.20 μs and time for one shared key generation is 81.00 and 158.40 μs. Similarly, the consumed power over and is 0.91 and 1.37 mW, respectively. The proposed coprocessor architecture outperforms state-of-the-art ECDH designs in terms of hardware resources.

FPGA-oriented lightweight multi-modal free-space detection network

For autonomous vehicles, free-space detection is an essential part of visual perception. With the development of multi-modal convolutional neural networks (CNNs) in recent years, the performance of driving scene semantic segmentation algorithms has been dramatically improved. Therefore most free-space detection algorithms are developed based on multiple sensors. However, multi-modal CNNs have high data throughput and contain a large number of computationally intensive convolution calculations, limiting their feasibility for real-time applications. Field Programmable Gate Arrays (FPGAs) provide a unique combination of flexibility, performance, and low power for these problems to accommodate multi-modal data and the computational acceleration of different compression algorithms. Network lightweight methods offer great assurance for facilitating the deployment of CNNs on such resource-constrained devices. In this paper, we propose a network lightweight method for a multi-modal free-space detection algorithm. We first propose an FPGA-friendly multi-modal free-space detection lightweight network. It comprises operators that FPGA prefers and achieves a 95.54 % MaxF score on the test set of KITTI-Road free-space detection tasks and 81 ms runtime when running on 700 W GPU devices. Then we present a pruning approach for this network to reduce the number of parameters in case the complete model exceeds the FPGA chip memory. The pruning is in two parts. For the feature extractors, we propose a data-dependent filter pruner according to the principle that the low-rank feature map contains less information. To not compromise the integrity of the multi-modal information, the pruner is independent for each modality. For the segmentation decoder, we apply a channel pruning approach to remove redundant parameters. Finally, we implement our designs on an FPGA board using 8-bit quantisation, and the accelerator achieves outstanding performance. A real-time application of scene segmentation on KITTI-Road is used to evaluate our algorithm, and the model achieves a 94.39 % MaxF score and minimum 14 ms runtime on 20W FPGA devices.

Latency-Aware Accelerator of SIMECK Lightweight Block Cipher

This article presents a latency-optimized implementation of the SIMECK lightweight block cipher on a field-programmable-gate-array (FPGA) platform with a block and key lengths of 32 and 64 bits. The critical features of our architecture include parallelism, pipelining, and a dedicated controller. Parallelism splits the digits of the key and data blocks into smaller segments. Then, we use each segmented key and data block in parallel for encryption and decryption computations. Splitting key and data blocks helps reduce the required clock cycles. A two-stage pipelining is used to shorten the critical path and to improve the clock frequency. A dedicated controller is implemented to provide control functionalities. For the performance evaluation of our design, we report implementation results for two different cases on Xilinx 7-series FPGA devices. For our case one, the proposed architecture can operate on 382, 379, and 388 MHz frequencies for Kintex-7, Virtex-7, and Artix-7 devices. On the same Kintex-7, Virtex-7, and Artix-7 devices, the utilized Slices are 49, 51, and 50. For one encryption and decryption computation, our design takes 16 clock cycles. The minimum power consumption is 172 mW on the Kintex-7 device. For the second case, we targeted the same circuit frequency of 50 MHz for synthesis on Kintex-7, Virtex-7, and Artix-7 devices. With minimum hardware resource utilization (51 Slices), the least consumed power of 13.203 mW is obtained for the Kintex-7 device. For proof-of-concept, the proposed SIMECK design is validated on the NEXYS 4 FPGA with the Artix-7 device. Consequently, the implementation results reveal that the proposed architecture is suitable for many resource-constrained cryptographic applications.

Design and Verification of Petri-Net-Based Cyber-Physical Systems Oriented toward Implementation in Field-Programmable Gate Arrays—A Case Study Example

This paper presents a novel design approach of a Petri-net-based cyber-physical system (CPS). The idea is oriented toward implementation in a field-programmable gate array (FPGA). The proposed technique permits error detection in the system at the early specification stage in order to reduce the time and prototyping cost of the CPS. Due to the state explosion problem, the traditional verification methods have exponential computational complexity. In contrast, we show that under certain assumptions, the proposed algorithm is able to detect possible errors in the system even in cubic O(|T|2|P|) time. Furthermore, all the required steps of the proposed design method are presented and discussed. The idea is illustrated by a real-life case study example of a traffic light crossroad. The system was modelled, analysed, implemented, and finally validated within the FPGA device (Virtex-5 family).

Computer Vision-Based Kidney’s (HK-2) Damaged Cells Classification with Reconfigurable Hardware Accelerator (FPGA)

In medical and health sciences, the detection of cell injury plays an important role in diagnosis, personal treatment and disease prevention. Despite recent advancements in tools and methods for image classification, it is challenging to classify cell images with higher precision and accuracy. Cell classification based on computer vision offers significant benefits in biomedicine and healthcare. There have been studies reported where cell classification techniques have been complemented by Artificial Intelligence-based classifiers such as Convolutional Neural Networks. These classifiers suffer from the drawback of the scale of computational resources required for training and hence do not offer real-time classification capabilities for an embedded system platform. Field Programmable Gate Arrays (FPGAs) offer the flexibility of hardware reconfiguration and have emerged as a viable platform for algorithm acceleration. Given that the logic resources and on-chip memory available on a single device are still limited, hardware/software co-design is proposed where image pre-processing and network training were performed in software, and trained architectures were mapped onto an FPGA device (Nexys4DDR) for real-time cell classification. This paper demonstrates that the embedded hardware-based cell classifier performs with almost 100% accuracy in detecting different types of damaged kidney cells.

S-Box Attack Using FPGA Reverse Engineering for Lightweight Cryptography

Since the use of lightweight cryptography for Internet of Things (IoT) security increases, it is necessary to inform significant threats to IoT devices through research on the attacks of lightweight cryptography. This article demonstrates successful attacks on six lightweight cryptographies: DESL, LBlock, TWINE, PRESENT, KLEIN, and LED, after investigating over 50 modern lightweight cryptographies built on SRAM field-programmable gate arrays (FPGAs). We first describe the fundamental procedure of an S-box attack to detect and manipulate S-box within the FPGA bitstream and then carefully customize the S-box attacks for each lightweight cryptography in order to weaken plaintext or key information. For practical analysis, a typical IoT platform based on Cortex-M0 operating at 50 MHz is implemented along with a variety of cryptography algorithms and design options on three Xilinx FPGA chips: Spartan-6, Artix-7, and Kintex Ultrascale. According to experimental results, the proposed attack successfully extracts the full 64-bit plaintext for DESL, LBlock, and TWINE. For KLEIN and LED, the full 64-bit keys are recovered, and for PRESENT, 80% of the 64-bit keys out of the total 80-bit keys are partially retrieved. We emphasize that the purpose of this article is not to provide attackers with a feasible attack strategy, but rather to raise awareness about the possibility of an attacker manipulating the lightweight cryptography on FPGA devices.

Exploiting HBM on FPGAs for Data Processing

Field Programmable Gate Arrays (FPGAs) are increasingly being used in data centers and the cloud due to their potential to accelerate certain workloads as well as for their architectural flexibility, since they can be used as accelerators, smart-NICs, or stand-alone processors. To meet the challenges posed by these new use cases, FPGAs are quickly evolving in terms of their capabilities and organization. The utilization of High Bandwidth Memory (HBM) in FPGA devices is one recent example of such a trend. In this article, we study the potential of FPGAs equipped with HBM from a data analytics perspective. We consider three workloads common in analytics-oriented databases and implement them on an FPGA showing in which cases they benefit from HBM: range selection, hash join, and stochastic gradient descent for linear model training. We integrate our designs into a columnar database (MonetDB) and show the trade-offs arising from the integration related to data movement and partitioning. We consider two possible configurations of the HBM, using a single and a dual clock version design. With the right design, FPGA+HBM-based solutions are able to surpass the highest performance provided by either a two-socket POWER9 1 system or a 14-core Xeon 2 E5 by up to 5.9× (range selection), 18.3× (hash join), and 6.1× (SGD).

An efficient reconfigurable peak cancellation model for peak to average power ratio reduction in orthogonal frequency division multiplexing communication system

<span lang="EN-US">The peak to average power ratio (PAPR) in orthogonal frequency division multiplexing (OFDM) communication system will be reduced using reconfigurable peak cancellation (RPC). RPC will also aid in improves the error vector magnitude (EVM) and reduces adjacent channel leakage ratio (ACLR) in OFDM communication system. The proposed RPC design methodology and practical implementation using field programmable gate array (FPGA) are discussed. The proposed RPC has been demonstrated using VIRTEX-7 XC7Z100 dual-core FPGA device with less hardware difficulty and minimum utilization of FPGA resources. The proposed RPC improves the efficiency of OFDM communication process by reducing complementary cumulative distribution function (CCDF) with respect to instantaneous power in dB. A comparison analysis was done between the existing selective mapping (SLM) method with proposed RPS method with respect FPGA resource utilization. The proposed RPC is implemented using VIRTEX-7 XC7Z100 dual-core FPGA device. Its effectively utilizing sub-carriers, fast Fourier transform (FFT) filter, bandwidth, and sampling frequency. Due to parallel switching operation, it reduces the PAPR, ACLR and improves EVM in OFDM signal with less hardware complexity.</span>

Soft Error Sensitivity Analysis Based on 40 nm SRAM-Based FPGA

Soft errors induced by radiation are the major reliability threat for SRAM-based field-programmable gate arrays (FPGAs). A more detailed analysis of the soft error sensitivity of the 40 nm SRAM-based FPGA was performed. Experimental methods for the configurable logic module, configure memory cells, and block RAM have been introduced for measuring the single event effects (SEEs) induced by alpha particles using a 241Am radiation source. The single event upset (SEU) and single event functional interrupt (SEFI) cross sections of different functional blocks have been calculated to discuss the failure mechanisms of the FPGA. The SEEs test results for the FPGA device based on the 40 nm CMOS process are significant.

Real-Time Force Reconstruction in a Transverse Dynamic Force Microscope

One major functionality of force microscopes is their ability to measure forces at a high sensitivity, thereby, allowing understanding of vital mechanisms: for instance, in bio-specimens. The investigation of a specimen’s viscoelasticity on nano-scale can have significant scientific impact, but has been inhibited by the lack of fast, comprehensive scanning instruments. In principle, transverse dynamic force microscopes (TDFMs) permit the measurement of interaction forces within delicate samples in a noncontact manner. The force measurements are reconstructed via complicated offline analysis in TDFMs, therefore, they can hardly be utilized as an online force measuring tool. This article introduces a novel integrated robust design for practical <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">scanning</i> using the TDFM system. The digital design is implemented in fixed-point arithmetic using field programmable gate array devices, thereby, permitting measurement of the interaction force at a high sampling rate. The novel digital design tackles different implementation issues achieving fast and robust force measuring performance. This enables a new <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">force-scan mode</i> for the TDFM, realizing for the first time, online force mapping of sample-surfaces in real-time.

Fused Architecture for Dense and Sparse Matrix Processing in TensorFlow Lite

In this article, we present a hardware architecture optimized for sparse and dense matrix processing in TensorFlow Lite and compatible with embedded-heterogeneous devices that integrate central processing unit and field-programmable gate array (FPGA) resources. The fused architecture for dense and sparse matrices design offers multiple configuration options that tradeoff parallelism and complexity, and uses a dataflow model to create four stages that read, compute, scale, and write results. All stages are designed to support TensorFlow Lite operations including asymmetric quantized activations, column-major matrix write, per-filter/per-axis bias values, and current scaling specifications. The configurable accelerator is integrated with the TensorFlow Lite inference engine running on the ARMv8 processor. We compare performance/power/energy with the state-of-the-art RUY software multiplication library showing up to 18× acceleration and 48× in dense and sparse modes, respectively. The sparse mode benefits from structural pruning to fully utilize the digital signal processing blocks present in the FPGA device.

Medical Oxygen Sensor Based on Acoustic Resonance Frequency Tracking Using FPGA

The aim of this study is to develop a noninvasive medical oxygen sensor using the acoustic resonance frequency tracking technique. To make it realize, the optimization of sound-resonance cavity based on an acoustic longitudinal mode is used as the sensing element for this sensor. A new method for resonance frequency tracking is presented by the phase difference comparison and calculation. Based on the relationships among the excitation and response signals of the sound-resonance cavity, the phase difference comparison and calculation algorithm had been used to automatically track the resonance frequency. The resonance frequency tracking is implemented by the field-programmable gate array (FPGA) device. The performance of the sensor is demonstrated by measuring the concentration of oxygen. The test results show that a sensitivity limit of 1000 ppm, a response time of 4 s, and detection capabilities over a broad concentration range from 1000 ppm to 100% have been demonstrated at one atmosphere. Results demonstrate that this work is expected to provide a new technical means for medical oxygen monitoring.

A study on the influence of dose rate on total ionizing dose effect of anti-fuse field programmable gate array—The irradiation damage is attenuated at low dose rate

The TID (total ionizing dose) in-situ experiments of LC1020B, an anti-fuse FPGA (Field Programmable Gate Array) device, were designed and carried out under different dose rates, and the influence of dose rate on the TID effect of FPGA was studied. The experimental results show that: 1) the TID irradiation failure of the FPGA under different dose rates has nothing to do with the input voltage parameter exceeding the standard. 2) with the decrease of cobalt source irradiation dose rate [171, 26.83, and 2.68 mGy(Si)/s], the TID effect failure dose threshold [168, 229, and 334 Gy(Si), respectively] of the FPGA gradually increased, showing obvious attenuation of low dose rate damage. Theoretical analysis suggests that, compared with the space charge limitation effect, the oxide charge annealing effect plays a dominant role, and longer irradiation time is beneficial to the oxide charge annealing. And based on the experimental data, an FPGA TID analytical model with power consumption current as the damage characterization parameter is established, which lays a foundation for scientific evaluation of radiation effect of anti-fuse FPGAs.

Improvement of Automotive Sensors by Migrating AUTOSAR End-to-End Communication Protection Library into Hardware

This paper explores new methods to increase the level of safety of data transfer between sensors and electronic control units (ECUs) in automotive communication. A new model of basic sensors to be used in automotive electronics is proposed. This model contains hardware modules that implement the end-to-end communication protection (E2E) mechanism, as defined by the Automotive Open System Architecture (AUTOSAR) standard. By adding this feature inside the sensors, it is possible that, in addition to increasing the safety level, these sensors can be directly connected to the network ECUs via standard communication buses (e.g., Local Interconnect Network (LIN), Controller Area Network (CAN), Flexray, etc.). This paper describes the model, design, and mapping (in a Field Programmable Gate Array device (FPGA)) of the hardware E2E module capable of generating the Cyclic Redundancy Code (CRC) and counter signal for a customized message. This message represents the output of the new sensor E2E module used in a safety communication as requested by the automotive E2E standard. The model is validated also by comparing the data output of the E2E hardware with the data output of the AUTOSAR software E2E library. Finally, future needs and directions are suggested in this area.

Power Line Communication Method for the Simultaneous Transmission of Power and Digital Data by Cascaded H-Bridge Converters

Power line communication (PLC) enables the interconnectivity and interoperability of distributed power production units in smart grids and microgrids by using existing cabling to monitor and control the overall power system. In this article, a novel PLC method for cascaded H-bridge converters is proposed, which is based on the use of the circuits of the individual power modules for the transmission of both power and digital information. Compared to the existing PLC approaches, the method proposed in this article combines the advantages of applicability to cascaded H-bridge structures with either a dc or an ac output, avoidance of using an additional power amplifier or coupling circuit for the transmission of information and independence from the implementation scale and the type of the power-supplied load. The design of both the proposed data transmitter and receiver units on field-programmable gate array devices is presented in the article. The proposed PLC system has been applied to an experimental prototype of a two-cell cascaded H-bridge inverter. The experimental results verified the successful transmission of telemetry data through the power converter circuit and their retrieval by a receiver attached in the power loop, along with the simultaneous transmission of power to the load.

Energy-Efficient Encoding for High-Speed Serial Interfaces

Energy consumption has become a bottleneck in modern integrated circuits (ICs) with a significant part of the energy spent on data communication. High-speed, serial interfaces are widely used, offering important advantages over parallel buses. The energy demand of source synchronous, serial buses can be effectively decreased by employing encoding techniques that reduce the bit transitions of the transmitted data stream. However, these techniques are not applicable for asynchronous interfaces, such as Peripheral Component Interconnect Express (PCIe), where frequent bit transitions are required to recover the clock at the receiver to maintain link integrity. Recognizing this fundamental trait, an encoding technique named serial tuned transition encoding (STTE) is proposed that regulates the number of transitions such that the clock can be reliably recovered, while the communication energy is lowered. The proposed scheme provides at least 25% decrease in energy for a short interposer-based interconnect compared to scrambling, which is typically used in serializer/deserializer (SerDes) devices. The link integrity is experimentally evaluated using both an electrical and an optical link that interconnect two field-programmable gate array (FPGA) devices. Results demonstrate that STTE successfully preserves link integrity as no errors are induced during transmission. In addition, STTE adjusts the number of transitions, thus allowing energy reduction and link integrity to be traded off.

UTC Synchronized Signal Generation for Synchrophasors and Sampled Values Measurements

This article describes two methods and circuits for generation of a signal synchronized to the Coordinated Universal Time (UTC) time scale. The signal is used as a sampling clock for a synchrophasor and Sampled Values generation. Both methods use a PPS (Pulse Per Second) pulse as a synchronization signal. In the first method, the synchronization procedure is implemented entirely in a Field Programmable Gate Array (FPGA) device. The second method uses a microcontroller and a Temperature Compensated Voltage Controlled Crystal Oscillator (TCVCXO). The common feature of the presented methods is that they are cost effective and use a minimal number of components. This paper presents the implementation details of both methods as well as the measurement results, which show that the accuracy of the synchronized signals in both procedures makes them suitable for use in synchrophasors and sampled values measurements.

FPGA-Based Implementation for Real-Time Epileptic EEG Classification Using Hjorth Descriptor and KNN

The EEG is one of the main medical instruments used by clinicians in the analysis and diagnosis of epilepsy through visual observations or computers. Visual inspection is difficult, time-consuming, and cannot be conducted in real time. Therefore, we propose a digital system for the classification of epileptic EEG in real time on a Field Programmable Gate Array (FPGA). The implemented digital system comprised a communication interface, feature extraction, and classifier model functions. The Hjorth descriptor method was used for feature extraction of activity, mobility, and complexity, with KNN was utilized as a predictor in the classification stage. The proposed system, run on a The Zynq-7000 FPGA device, can generate up to 90.74% accuracy in normal, inter-ictal, and ictal EEG classifications. FPGA devices provided classification results within 0.015 s. The total memory LUT resource used was less than 10%. This system is expected to tackle problems in visual inspection and computer processing to help detect epileptic EEG using low-cost resources while retaining high performance and real-time implementation.

Hardware Efficient Hybrid Pseudo-Random Bit Generator Using Coupled-LCG and Multistage LFSR with Clock Gating Network

A new method for the generation of pseudo-random bits, based on a coupled-linear congruential generator (CLCG) and two multistage variable seeds linear feedback shift registers (LFSRs) is presented. The proposed algorithm dynamically changes the value of the seeds of each linear congruential generator (LCG) by utilizing the multistage variable seeds LFSR. The proposed approach exhibits several advantages over the pseudo-random bit generator (PRBG) methods presented in the literature. It provides low hardware complexity and high-security strength while maintaining the minimum critical path delay. Moreover, this design generates the maximum length of pseudo-random bit sequence with uniform clock latency. Furthermore, to improve the critical path delay, one more architecture of PRBG is proposed in this work. It is based on the combination of coupled modified-LCG with two variable seeds multistage LFSRs. The modified LCG block is designed by the two-operand modulo adder and XOR gate, rather than the three-operands modulo adder and shifting operation, while it maintains the same security strength. The clock gating network (CGN) is also used in this work to minimize the dynamic power dissipation of the overall PRBG architecture. The proposed architectures are implemented using Verilog HDL and further prototyped on commercially available field-programmable gate array (FPGA) devices Virtex-5 and Virtex-7. The realization of the proposed architecture in this FPGA device accomplishes an improved speed of PRBG, which consumes low power with high randomness compared to existing techniques. The generated binary sequence from the proposed algorithms has been verified for randomness tests using NIST statistical test suites.