Field Programmable Gate Array Device Research Articles

A fast and scalable architecture to run convolutional neural networks in low density FPGAs

Deep learning and, in particular, convolutional neural networks (CNN) achieve very good results on several computer vision applications like security and surveillance, where image and video analysis are required. These networks are quite demanding in terms of computation and memory and therefore are usually implemented in high-performance computing platforms or devices. Running CNNs in embedded platforms or devices with low computational and memory resources requires a careful optimization of system architectures and algorithms to obtain very efficient designs. In this context, Field Programmable Gate Arrays (FPGA) can achieve this efficiency since the programmable hardware fabric can be tailored for each specific network. In this paper, a very efficient configurable architecture for CNN inference targeting any density FPGAs is described. The architecture considers fixed-point arithmetic and image batch to reduce computational, memory and memory bandwidth requirements without compromising network accuracy. The developed architecture supports the execution of large CNNs in any FPGA devices including those with small on-chip memory size and logic resources. With the proposed architecture, it is possible to infer an image in AlexNet in 4.3 ms in a ZYNQ7020 and 1.2 ms in a ZYNQ7045.

Area and power‐efficient variable‐length fast Fourier transform for MR‐OFDM physical layer of IEEE 802.15.4‐g

The authors present a novel 16/32/64/128-point single-path delay feedback pipeline fast Fourier transform (FFT) architecture targeting the multi-rate and multi-regional orthogonal frequency division multiplexing (MR-OFDM) physical layer of IEEE 802.15.4-g. The proposed FFT architecture employs a mixed-radix algorithm to significantly reduce the number of complex multipliers. It utilises a configurable complex constant multiplier structure instead of a fixed constant multiplier to efficiently conduct W 32 , W 64 , and W 128 twiddle factor multiplication. A hardware-sharing mechanism has also been formulated to reduce the memory space requirements of the proposed 16/32/64/128-point FFT computation scheme. The proposed design is implemented in Xilinx Virtex-5 and Altera's field-programmable gate array devices. For the computation of 128-point FFT, the proposed mixed-radix FFT architecture significantly reduces the hardware cost in comparison with existing FFT architecture. The proposed FFT architecture is also implemented by adopting the 90 nm complementary metal-oxide-semiconductor technology with a supply voltage of 1 V. Post-synthesis results reveal that the design is efficient in terms of gate count and power consumption, compared to earlier reported designs. The proposed variable-length FFT architecture gate count is 22.3K and consumes 3.832 mW, while the word-length is 12-bits and can be efficiently useful for the IEEE 802.15.4-g standard.

FPGA-based neural network accelerators for millimeter-wave radio-over-fiber systems.

With rapidly developing high-speed wireless communications, the 60 GHz millimeter-wave (mm-wave) frequency range has attracted extensive interests, and radio-over-fiber (RoF) systems have been widely investigated as a promising solution to deliver mm-wave signals. Neural networks have been proposed and studied to improve the mm-wave RoF system performances at the receiver side by suppressing both linear and nonlinear impairments. However, previous studies of neural networks in mm-wave RoF systems all focus on the use of off-line processing with high-end GPUs or CPUs, which are not practical for low power-consumption, low-cost and limited computation platform applications. To solve this issue, in this paper we investigate neural network hardware accelerator implementations for mm-wave RoF systems for the first time using the field programmable gate array (FPGA), taking advantage of the low power consumption, parallel computation, and reconfigurablity features of FPGA. Both the convolutional neural network (CNN) and binary convolutional neural network (BCNN) hardware accelerators are demonstrated. In addition, to satisfy the low-latency requirement in mm-wave RoF systems and to enable the use of low-cost compact FPGA devices, a novel inner parallel computation optimization method for implementing CNN and BCNN on FPGA is proposed. It is shown that compared with the popular embedded processor (ARM Cortex A9) execution latency, the proposed FPGA-based hardware accelerator reduces the processing delay in mm-wave RoF systems by about 99.45% and 92.79% for CNN and BCNN, respectively. Compared with non-optimized FPGA implementations, results show that the proposed inner parallel computation method reduces the processing latency by about 44.93% and 45.85% for CNN and BCNN, respectively. In addition, compared with the GPU implementation, the latency of CNN implementation with the proposed optimization method is reduced by 85.49%, while the power consumption is reduced by 86.91%. Although the latency of BCNN implementation with the proposed optimization method is larger compared with the GPU implementation, the power consumption is reduced by 86.14%. The demonstrated FPGA-based neural network hardware accelerators provide a promising solution for mm-wave RoF systems.

A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA

Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

Efficient Implementation of Multiple Time Coding Lines-Based TDC in an FPGA Device

This article presents two principles that make multiple time coding lines (TCLs)-based time-to-digital converter (TDC) implementation in field-programmable gate array (FPGA) device more efficient. A pseudo-segmented delay line allows for saving many logical resources by effective utilization of programmable logic block elements. A chopped TCL improves measurement resolution and precision and takes advantage of a global clock network skew. Both designs were implemented in a Kintex-7 FPGA chip, manufactured by Xilinx in 28-nm CMOS process, and compared to well-known TCL solutions, that is, a commonly used “plain” architecture and a tuned delay line. All four designs, working in a single and multiple configurations, were tested and compared in terms of resource utilization, measurement resolution, and precision. Designed TDCs employed in a one channel timestamps-based interpolating time counter allowed to get mean resolution of 1 ps and precision even below 4 ps using up to ten TCLs.

Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

This paper proposes a triple time-to-digital converter (TDC) for a field-programmable gate array (FPGA) platform with dual operation modes. First, the proposed triple-TDC employs the real-time calibration circuit followed by the traditional tapped delay line architecture to improve the environmental effect for the application of multiple TDCs. Second, the triple modular redundancy scheme is used to deal with the uncertainty in the FPGA device for improving the linearity for the application of a single TDC. The proposed triple-TDC is implemented in a Xilinx Virtex-5 FPGA platform and has a time resolution of 40 ps root mean square for multi-mode operation. Moreover, the ranges of differential nonlinearity and integral nonlinearity can be improved by 56 % and 37 % , respectively, for single-mode operation.

A Novel High-Precision Synchronous Sampling Mechanism for Distributed Test System Based on Optical Fiber Network and Low-Cost Field-Programmable Gate Array

In this paper, we propose a distributed test system based on optical fiber network with multiple devices. In order to resolve the data sampling synchronicity problems, a novel synchronous sampling mechanism is developed to achieve high-precision sampling synchronicity among data acquisition devices with relatively low-cost hardware. First, we present the design of the system based on optical fiber network and the mechanism implemented in Field-Programmable Gate Array (FPGA) devices. Then, the device clocks are calibrated to run on a same frequency using a clock-disciplining algorithm for hardware implementation. In addition, propagation delays, which are used for the synchronous errors compensation during data analysis, are precisely measured using a high-precision time interval measurement approach based on delay-chain loop comparison method. A series of experiments on a real test system demonstrate the effectiveness of the proposed models and methods, and the mechanism has been employed in a general-purpose reprogrammable device cyclone-II (Altera).

PARALLEL PIPELINED MULTI RADIX VARIABLE LENGTH FAST FOURIER TRANSFORM ARCHITECTURE

There is an enormous demand for high speed data communication or high speed internet using Long Term Evolution (LTE) or LTE-Advanced communication methods. To achieve the high speed data rate in the receiver side, it is necessary to achieve high throughput in the Fast Fourier transform (FFT) architecture. Hence there is demand to improve the throughput of the FFT architectures used for high speed data communication. The FFT architecture is designed and optimized for LTE-A applications. However, the high throughput has been achieved by sacrificing hardware resources of the Field Programmable Gate Array (FPGA). Many fixed and variable length FFT processors are proposed by the researchers with improved performance focusing either on algorithmic modifications, novel architectural optimizations or radix selection. Among these FFT processors, the goal and main objectives of this paper are: 1. To design and implement a pipelined FFT architecture to give high throughput for LTE-A MIMO applications 2. To develop an intellectual property (IP) core for FFT computation with variable FFT size 3. To propose a parallel implementation to increase the performance of LTE-A baseband processing system. In an Orthogonal Frequency Division Multiplexing (OFDM) baseband communication system, FFT operation is one of the highest computationally serious tasks which directly influence the communication system performance factor. The baseband hardware has to be capable as well as efficient enough to calculate FFT in specific timing restrictions. Thus, the parallel pipelined multi radix Variable Length FFT architectures for LTE-A Multiple-Input-Multiple-Output (MIMO) applications have been designed. The proposed FFT architecture delivers a throughput of 550 MSPS at the maximum clock rate of 550 MHz. The proposed FFT support the FFT length of 64, 128, 256, 512, 1024 and 2048 for LTE-Advanced MIMO standard. The proposed FFT architecture has been implemented in Xilinx Artix-7 FPGA device and the performance metrics have been analysed. Even though the proposed FFT architecture consumes additional Block-RAMs (BRAM) and quite an amount of Xilinx-Xtreme Digital Signal Processor (DSP)/ DSP48 resources, the Power Delay Product (PDP) of the proposed FFT is excellent compared to the existing FFT architectures. The proposed multi radix mixed 2/3/5 parallel pipelined 2048 point FFT architectures exhibits very less latency of 11.382 µs at 550 MHz clock frequency compared to the existing system with the latency of 56.88 µs at 200 MHz clock frequency. Moreover, the designed FFT architecture utilizes 96 Xilinx Xtreme DSP blocks 25040 clock cycles to complete the FFT operation with an excellent throughput of 2200 MSPS with FFT computation time of 45.528 µs at the clock frequency of 550 MHz for the 4x4 MIMO- OFDM architecture. Therefore, the designed FFT provides high throughput rate in order to meet the modern wireless standard specifications. The proposed FFT architecture outperforms well in terms high throughput, low latency and better PDP with extra hardware as trade-off for both for Single FFT and for MIMO technology.

Dynamic partial reconfiguration enchanced with security system for reduced area and low power consumption

Field-programmable gate arrays (FPGAs) have travelled far from just being utilized as glue logic to an entire system solution. This is mostly due to their generalized re-configurable nature, lower non-recurring engineering (NRE) expense, and also fast time to market. Owing to the reconfigurable nature of FPGA, a new field called reconfigurable computing that can change the circuit configuration after hardware production came into existence. Application of re-configurable computing for self-adaptive hardware allows hardware to get adapt to various environmental conditions and different needs by swapping or loading disparate computational modules. This work proposes an effectual design methodology (enhanced DPR security system (EDPRSS)) utilized to execute high performance FPGA device in respect of low power consumption along with security for the area reduction. In the proposed technique, hash code generation (HCG) and encryption hardware accelerators can well be dynamically produced on FPGA utilizing partial re-configuration as stated by the application requisites. The system is competent to swap in or swap out the equivalent hardware accelerator during run time, which in turn diminishes the power and area. Here, 2 re-configurable partitions are produced for encryption and also HCG algorithm. Experiential outcomes proved that the proposed technique proffers better performance when contrasted to the other conventional systems.

Parallel architecture of power‐of‐two multipliers for FPGAs

This research work presents a novel approach to design efficient power-of-two multipliers on modern field-programmable gate arrays (FPGA) devices. Several ways of exploiting fixed-point power-of-two multiplications have been recently demonstrated to reduce the computational complexity of several computationally intensive applications, such as computer vision, deep learning, and many others. Modern FPGA devices provide speed-optimised intellectual property (IP) cores based on embedded modules, such as digital signal processing blocks, and area-optimised IP cores based on reconfigurable logic resources, such as look-up tables and flip-flops. Unfortunately, due either to their limited available amount or to their limited running frequency, these IP cores do not allow the overall computational capability offered by an FPGA device to be completely exploited. While the speed-optimised version of the multiplier proposed here is fast enough to increase the number of operations performed per second by up to 4.3 times, with respect to the conventional designs, its area-optimised implementation reduces resources requirements and energy consumption by up to 22 and 40%.

Low-Complexity Nonlinear Self-Inverse Permutation for Creating Physically Clone-Resistant Identities

New large classes of permutations over ℤ 2 n based on T-Functions as Self-Inverting Permutation Functions (SIPFs) are presented. The presented classes exhibit negligible or low complexity when implemented in emerging FPGA technologies. The target use of such functions is in creating the so called Secret Unknown Ciphers (SUC) to serve as resilient Clone-Resistant structures in smart non-volatile Field Programmable Gate Arrays (FPGA) devices. SUCs concepts were proposed a decade ago as digital consistent alternatives to the conventional analog inconsistent Physical Unclonable Functions PUFs. The proposed permutation classes are designed and optimized particularly to use non-consumed Mathblock cores in programmable System-on-Chip (SoC) FPGA devices. Hardware and software complexities for realizing such structures are optimized and evaluated for a sample expected target FPGA technology. The attained security levels of the resulting SUCs are evaluated and shown to be scalable and usable even for post-quantum crypto systems.

Advanced superior execution time optimal time-frequency filter suitable for non-linear FM signals estimation

Optimal time-frequency (TF) filter suitable for non-linear frequency-modulated (FM) signals estimation is developed. It is developed to suppress some flaws of the recent state-of-the-art signal adaptive and fully pipelined filtering solutions and, therefore, is based on a new real-time procedure for the filter's region of support estimation, also proposed here. The proposed filter shows superior execution time performances and optimal calculation and hardware complexity properties, so it retains all desirable properties of the signal adaptive solution and the fully pipelined one, but also extends their applicability to the non-linear FM signals. The filter is implemented on the field-programmable gate array (FPGA) device and is proven by testing on real non-stationary multicomponent noisy signals.

Dynamic Bus Voltage Reconfiguration in a Two-Stage Multiphase Converter for Fast Transient

This article proposes a dynamic bus voltage transition method in a two-stage multiphase buck converter for 48-V-to-point-of-load (PoL) applications. The proposed topology uses a bank of precharged switching capacitors at the output of the first-stage buck converter. This configuration helps to achieve an immediate intermediate bus voltage transition while supplying a (second-stage) multiphase buck converter. This can substantially speed up a large-signal transient recovery by adjusting the bus voltage to its highest voltage level. Thereafter, near steady state, the bus voltage is set to its (lower) optimum value for improving the overall efficiency of the two-stage architecture. A higher bus voltage can reduce the output capacitance for the second-stage while retaining the (voltage) undershoot within the desired limit, which can reduce recovery time and current overshoot during a step-reference transient. The first stage operates in the open loop, while the second stage uses mixed-signal current mode control using a field-programmable gate array (FPGA) device. A hardware prototype of the proposed architecture is made, and an improved performance is demonstrated using simulation and experimental results.

Towards cloud energy metering system with 32 bit FPGA device architecture

Cloud based Advanced Metering Infrastructure (CAMI) is the next digital future for energy management (EM). Various efforts on EM capabilities are mainly skewed towards embedded device architectures that support non-concurrent execution. This paper presents cloud energy metering system (CEMS) using high speed 32 bit field programmable gate array (FPGA) device. The architectural framework for energy tracking and profile measurement in CEMS is presented. This aims at accurate metering with demand side management (DSM). An application context that supports an EM architecture is highlighted. The contextual CEMS features energy monitoring in distributed energy utilities such as solar generators, wind and energy storage sources. Process integration with Cloud based Internet for real-time energy reading is achieved through the FPGA synthesis to provide end-to-end energy analytics. CEM prototype (Xilinx FPGA) running on a wireless open-access research platform supports management of large historical data-sets from the current data up to the last granular interval, hourly, daily, monthly and yearly dataset captures. The system provides the low latency datasets in both tabular and graphical forms for end-user visualization of energy consumption patterns. In the experimental setup, three case scenarios demonstrate how the metering system executes fast edge computing profiling, thereby providing data-visualization services to end-users. The results show the Avg. Latency time for CAMI household 1, 2 and 3 respectively. In case 1, the average latencies for actual and measured (proposed CAMI) are 75% and 25% respectively. In case 2 and case 3, this gave 66.67% and 33.33% respectively. Clearly, the proposed CAMI offers lower latency for all scenarios of energy consumption metering usage.Keywords: Advanced Metering, Energy management, Cyber-physical systems, Cloud Computing, IoT, Fog. 1.0 INTRODUCTION

Bio-Inspired Approaches to Safety and Security in IoT-Enabled Cyber-Physical Systems.

Internet of Things (IoT) and Cyber-Physical Systems (CPS) have profoundly influenced the way individuals and enterprises interact with the world. Although attacks on IoT devices are becoming more commonplace, security metrics often focus on software, network, and cloud security. For CPS systems employed in IoT applications, the implementation of hardware security is crucial. The identity of electronic circuits measured in terms of device parameters serves as a fingerprint. Estimating the parameters of this fingerprint assists the identification and prevention of Trojan attacks in a CPS. We demonstrate a bio-inspired approach for hardware Trojan detection using unsupervised learning methods. The bio-inspired principles of pattern identification use a Spiking Neural Network (SNN), and glial cells form the basis of this work. When hardware device parameters are in an acceptable range, the design produces a stable firing pattern. When unbalanced, the firing rate reduces to zero, indicating the presence of a Trojan. This network is tunable to accommodate natural variations in device parameters and to avoid false triggering of Trojan alerts. The tolerance is tuned using bio-inspired principles for various security requirements, such as forming high-alert systems for safety-critical missions. The Trojan detection circuit is resilient to a range of faults and attacks, both intentional and unintentional. Also, we devise a design-for-trust architecture by developing a bio-inspired device-locking mechanism. The proposed architecture is implemented on a Xilinx Artix-7 Field Programmable Gate Array (FPGA) device. Results demonstrate the suitability of the proposal for resource-constrained environments with minimal hardware and power dissipation profiles. The design is tested with a wide range of device parameters to demonstrate the effectiveness of Trojan detection. This work serves as a new approach to enable secure CPSs and to employ bio-inspired unsupervised machine intelligence.

Spin Me Right Round Rotational Symmetry for FPGA-Specific AES: Extended Version

The effort in reducing the area of AES implementations has largely been focused on application-specific integrated circuits (ASICs) in which a tower field construction leads to a small design of the AES S-box. In contrast, a naive implementation of the AES S-box has been the status-quo on field-programmable gate arrays (FPGAs). A similar discrepancy holds for masking schemes—a well-known side-channel analysis countermeasure—which are commonly optimized to achieve minimal area in ASICs. In this paper, we demonstrate a representation of the AES S-box exploiting rotational symmetry which leads to a 50% reduction in the area footprint on FPGA devices. We present new AES implementations which improve on the state-of-the-art and explore various trade-offs between area and latency. For instance, at the cost of increasing 4.5 times the latency, one of our design variants requires 25% less look-up tables (LUTs) than the smallest known AES on Xilinx FPGAs by Sasdrich and Güneysu at ASAP 2016. We further explore the protection of such implementations against side-channel attacks. We introduce a generic methodology for masking any n-bit Boolean functions of degree t with protection order d. The methodology is exact for first-order and heuristic for higher orders. Its application to our new construction of the AES S-box allows us to improve previous results and introduce the smallest first-order masked AES implementation on Xilinx FPGAs, to date.

DSP-Efficient Hardware Acceleration of Convolutional Neural Network Inference on FPGAs

Field-programmable gate array (FPGA)-based accelerators for convolutional neural network (CNN) inference have received significant attention in recent years. The reported designs tend to adopt a similar underlying approach based on multiplier-accumulator (MAC) arrays, which yields strong demand for the available on-chip DSP blocks, while leaving FPGA logic and memory resources underutilized. The practical outcome is that the computational roof of the accelerator is bound by the number of DSP blocks offered by the target FPGA. In addition, integrating the CNN accelerator with other functional units that may also need DSP blocks would degrade the inference performance. Leveraging the robustness of inference accuracy to limited arithmetic precision, we propose a transformation to the convolution computation, which leads to transformation of the accelerator design space and relaxes the pressure on the required DSP resources. Through analytical and empirical evaluations, we demonstrate that our approach enables us to strike a favorable balance between utilization of the FPGA on-chip memory, logic, and DSP resources, due to which, our accelerator considerably outperforms state of the art. We report the effectiveness of our approach on a variety of FPGA devices, including Cyclone-V, Stratix-V, and Arria-10, which are used in large number of applications, ranging from embedded settings to high performance computing. Our proposed technique yields 1.5x throughput improvement and 4x DSP resource reduction compared to the best frequency domain convolution-based accelerator, and 2.5x boost in raw arithmetic performance and 8.4x saving in DSPs compared to a state-of-the-art sparse convolution-based accelerator.

Measurement of the PMSM Current with a Current Transducer with DSP and FPGA

In the present work, two approaches for the phase current measurement of a permanent magnet synchronous motor (PMSM) were compared. The measured phase current was distorted by glitches, and a software method to eliminate these glitches was necessary. An averaging of samples was carried out, and the experimental results indicated that averaging was essential for further calculations. Moreover, the PMSM operated smoothly, and the difference between the set point and the actual speed was reduced for the full range of loads from the free run up to a full load. The increasing popularity of field-programmable gate array (FPGA) devices has encouraged developments in PMSM controllers using a direct hardware approach and the classic software approach utilizing a digital signal processor unit. In this study, the selected performance of TMS320F2812 and Spartan-3E were compared. This paper proposes an original adaptive correction method for a current transducer.

FPGA-Based Lightweight Hardware Architecture of the PHOTON Hash Function for IoT Edge Devices

The design of cryptographic engines for the Internet of Things (IoT) edge devices and other ultralightweight devices is a crucial challenge. The emergence of such resource-constrained devices raises significant challenges to current cryptographic algorithms. PHOTON is an ultra-lightweight cryptographic hash function targeting low-resource devices. The currently implemented hardware architectures of PHOTON hash function utilize a large amount of resources and have low operating frequencies with a low rate of throughputs. Maximum operating frequency and throughput of PHOTON architecture can be improved but at the cost of larger area utilization. Therefore, to improve the area-performance trade-offs of PHOTON hash function, an iterative architecture is implemented in this work. The concern is with the most lightweight version of PHOTON hash function with the hash size of 80 bits. It is implemented and verified on several Xilinx and Altera Field Programmable Gate Array (FPGA) devices using their synthesis and simulation tools. Low-cost and high-processing FPGA devices were both considered. The design is optimized for performance, whereas the area utilization is also taken into consideration. The overall performance and logic utilization are benchmarked with the existing implementations. The results show an improvement rate of 10.26% to 51.04% in the speed performance and a reduction rate of 7.55% to 60.64% in area utilization compared to existing implementations of PHOTON hash functions.

A hybrid bio-inspired optimisation approach for wirelength minimisation of hardware tasks placement in field programmable gate array devices

In computer-aided design (CAD) flow of VLSI circuits, placement process is an NP-complete problem which requires an optimisation approach to obtain the system performance better. The main objective of placement is to reduce the wire length between the tasks with zero overlap. Fast response and better convergence algorithms are required to meet these desires. In this regard, bio-inspired optimisation algorithms such as genetic algorithm (GA) and particle swarm optimisation (PSO) algorithm have been considered. By using the salient features of these two algorithms, the optimised solution for placement problem has been obtained. The concept of GA has been applied followed by genetic algorithm to obtain optimised result. For experimentation, various directed data flow graphs (DDFGs) are randomly generated and the comparison is made between the GA, PSO and hybrid (GA-PSO) methods. The hybrid approach using GA-PSO produces better experimental results in wire length minimisation and, hence outperforms than the others.