Efficient Implementation of Multiple Time Coding Lines-Based TDC in an FPGA Device

Abstract

This article presents two principles that make multiple time coding lines (TCLs)-based time-to-digital converter (TDC) implementation in field-programmable gate array (FPGA) device more efficient. A pseudo-segmented delay line allows for saving many logical resources by effective utilization of programmable logic block elements. A chopped TCL improves measurement resolution and precision and takes advantage of a global clock network skew. Both designs were implemented in a Kintex-7 FPGA chip, manufactured by Xilinx in 28-nm CMOS process, and compared to well-known TCL solutions, that is, a commonly used “plain” architecture and a tuned delay line. All four designs, working in a single and multiple configurations, were tested and compared in terms of resource utilization, measurement resolution, and precision. Designed TDCs employed in a one channel timestamps-based interpolating time counter allowed to get mean resolution of 1 ps and precision even below 4 ps using up to ten TCLs.