Field Programmable Gate Array Architecture Research Articles

SymbiFlow and VPR: An Open-Source Design Flow for Commercial and Novel FPGAs

As the benefits of Moore's Law diminish, computing performance, and efficiency gains are increasingly achieved through specializing hardware to a domain of computation. However, this limits the hardware's generality and flexibility. Field-programmable gate arrays (FPGAs), microchips which can be reprogrammed to implement arbitrary digital circuits, enable the benefits of specialization while remaining flexible. A challenge to using FPGAs is the complex computer-aided design flow required to efficiently map a computation onto an FPGA. Traditionally, these design flows are closed-source and highly specialized to a particular vendor's devices. We propose an alternate data-driven approach, which uses highly adaptable and retargettable open-source tools to target both commercial and research FPGA architectures. While challenges remain, we believe this approach makes the development of novel and commercial FPGA architectures faster and more accessible. Furthermore, it provides a path forward for industry, academia, and the open-source community to collaborate and combine their resources to advance FPGA technology.

OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs

Demanded by ever-evolving data processing algorithms, field-programmable gate arrays (FPGAs) have become essential components of modern computing systems, thanks to their reconfigurable and distributed computing capabilities. However, FPGAs are among the very few integrated chips that still require long development cycles and high human efforts, even for industrial vendors. In this article, we introduce OpenFPGA, an open-source framework that can automate and significantly accelerate the development cycle of customizable FPGA architectures. OpenFPGA allows users to customize their FPGA architectures down to circuit-level details using a high-level architecture description language and autogenerate associated Verilog netlists which can be used in a backend flow to generate production-ready layouts. A generic Verilog-to-Bitstream generator is also provided, allowing end-users to implement practical applications on any FPGAs that OpenFPGA can support. Using OpenFPGA, we demonstrate less than 24-h layout generation of two FPGA fabrics, which are based on a Stratix-like architecture built with a commercial 12-nm standard cell library and 40-nm custom cells, respectively.

VTR 8

Developing Field-programmable Gate Array (FPGA) architectures is challenging due to the competing requirements of various application domains and changing manufacturing process technology. This is compounded by the difficulty of fairly evaluating FPGA architectural choices, which requires sophisticated high-quality Computer Aided Design (CAD) tools to target each potential architecture. This article describes version 8.0 of the open source Verilog to Routing (VTR) project, which provides such a design flow. VTR 8 expands the scope of FPGA architectures that can be modelled, allowing VTR to target and model many details of both commercial and proposed FPGA architectures. The VTR design flow also serves as a baseline for evaluating new CAD algorithms. It is therefore important, for both CAD algorithm comparisons and the validity of architectural conclusions, that VTR produce high-quality circuit implementations. VTR 8 significantly improves optimization quality (reductions of 15% minimum routable channel width, 41% wirelength, and 12% critical path delay), run-time (5.3× faster) and memory footprint (3.3× lower). Finally, we demonstrate VTR is run-time and memory footprint efficient, while producing circuit implementations of reasonable quality compared to highly-tuned architecture-specific industrial tools—showing that architecture generality, good implementation quality, and run-time efficiency are not mutually exclusive goals.

Pearl: Performance-Aware Wear Leveling for Nonvolatile FPGAs

Since static random access memory (SRAM)-based field-programmable gate array (FPGA) has limited density and comparatively high leakage power, researchers have proposed FPGA architectures based on emerging nonvolatile memories (NVMs) to satisfy the requirements of data-intensive and low-power applications. Among all components, block random access memory (BRAM) has the severest endurance problem in FPGA. Unluckily, traditional wear leveling (TWL) strategies cannot be directly applied to nonvolatile FPGA because it may induce large performance overhead. In this article, we propose performance-aware wear leveling schemes for nonvolatile FPGA to improve its lifetime. Two strategies pertaining to coarse-grained wear leveling (C-Pearl) and fine-grained wear leveling (F-Pearl) are developed to balance inter-BRAM and intra-BRAM writes. Procedures, including static analysis, wear leveling-guided placement, and reconfiguration are discussed. A supportive circuit design is proposed, too. The evaluation shows that C-Pearl and F-Pearl can achieve 34% and 46% higher lifetime improvement and simultaneously 8% and 11% lower performance overhead than TWL.

An Efficient Implementation of Divergence State Estimation with Biogeography-Based Optimization (DSEBBO) Framework in FPGA-Based Multiprocessor System

In recent years, Field Programmable Gate Array (FPGA) has different, and novel combinations of soft and hard cores embedded with accelerators in the same chip. At present, “Heterogeneous Multiprocessor System-on-Chip” technology meets the needs of the FPGA architecture as it not only consumes less space but also its design is implemented to enhance the performance resulting in decreased power consumption. However, traditional approaches can work within a limited range of values incurring high-power consumption, and they need substantial hardware resources involving complex procedures. In our proposed work, the combination of Graph Theory Estimator and Divergence State Estimation with Biogeography-Based Optimization (DSEBBO) is introduced. The principle notion of this proposed scheme is to optimize the required area resources and power consumption of the overall architecture by exploring the design space in a minimal time. The architecture uses a less number of hardware resources with a better outcome. The performances such as the latency, power consumption, delay, area and data rate are achieved better than the traditional works, and it is also application-aware with a multitask system. While comparing the outcome with the conventional asymmetric heterogeneous MPSoC method, the new DSEBBO design exhibits the performance improvement of 26.87% in data rate, and 37.18% reduction in average power consumption and 63.61% reduction in delay analysis under various traffic scenarios.

Recent Results on the Implementation of a Burst Error and Burst Erasure Channel Emulator Using an FPGA Architecture

The behaviour of a transmission channel may be simulated using the performance abilities of current generation multiprocessing hardware, namely, a multicore Central Processing Unit (CPU), a general purpose Graphics Processing Unit (GPU), or a Field Programmable Gate Array (FPGA). These were investigated by Cullinan et al. in a recent paper (published in 2012) where these three devices capabilities were compared to determine which device would be best suited towards which specific task. In particular, it was shown that, for the application which is objective of our work (i.e., for a transmission channel simulation), the FPGA is 26.67 times faster than the GPU and 10.76 times faster than the CPU. Motivated by these results, in this paper we propose and present a direct hardware emulation. In particular, a Cyclone II FPGA architecture is implemented to simulate a burst error channel behaviour, in which errors are clustered together, and a burst erasure channel behaviour, in which the erasures are clustered together. The results presented in the paper are valid for any FPGA architecture that may be considered for this scope.

Hardware-Assisted Simulation of Voltage-Behind-Reactance Models of Electric Machines on FPGA

This paper studies the acceleration of numerical simulations executed on Field-Programmable Gate Arrays (FPGAs) for electric machines presented by voltage-behind-reactance (VBR) models. In VBR models, the stator dynamics are modeled in abc coordinates, while the rotor dynamics are formulated in qd reference frame. Both induction motors and synchronous generators, operating without and with magnetic saturation, are considered. Once VBR models of these machine types are reviewed, their dynamic models are discretized using Runge-Kutta numerical routines. The detailed mapping of such discrete models to FPGA is provided using High-Level Synthesis, which directly converts untimed descriptions into VHDL or Verilog. An automated method finds the fastest FPGA architecture by finding the best set of synthesis options. Experimental results show that our FPGA-based acceleration flow leads to about 92-168 times average simulation speed-up for various machine types compared to the MATLAB simulation.

An FPGA-Based Accelerated Optimization Algorithm for Real-Time Applications

Many modern applications, such as industrial control, image processing and machine learning, are based on optimization algorithms that must solve compute-intensive problems under real-time constraints taking into account real-world parameters that evolve in time. Among others, evolutionary algorithms (EAs) are increasingly used in real-time applications to solve such complex optimization problems. Moreover, Field Programmable Gate Arrays (FPGAs) have been proved an effective platform for the implementation of these algorithms satisfying real-time and low-power requirements. In this paper, we study the FPGA-based acceleration of the Big Bang-Big Crunch (BB-BC) algorithm. BB-BC is an optimization method inspired by the corresponding evolutionary theory of the universe [1]. The BB-BC method is performed in two phases: in the Bing Bang phase, similarly to other Genetic Algorithms (GAs) it generates a random population of candidate solutions, while in the Big Crunch phase it shrinks these candidates around an optimal point. It has been shown that the BB-BC method outperforms classical GA algorithms for several optimization problems in terms of convergence speed. We show that the BB-BC algorithm does not suffer from the design limitations of the classical GAs that impede the performance of their hardware-based accelerators. We propose an efficient fully pipelined design of both BB-BC phases and a parallel scheme which integrates several BB-BC pipelined engines to improve system performance. We implement the proposed FPGA-based accelerator on a Xilinx Virtex-5 development board for three different fitness functions and compare the execution time against its software counterpart (in C language) and a CUDA program running on a massively parallel computing platform (GPU). We also compare the proposed optimized FPGA architecture with an RTL design generated by a high-level synthesis (HLS) design flow. We propose an Adaptive Neuro-fuzzy Inference System (ANFIS) model for fitness function approximation method to reduce the execution latency of complex fitness functions. We also demonstrate the efficiency of the proposed FPGA architecture on an image search problem, finding the darkest pixel of a grey image. The experimental results show that the proposed approach achieves significant speedup compared to the other software versions of the BB-BC algorithm and converges much faster than a typical GA algorithm making it an ideal solution for real-time embedded applications.

Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems

Field programmable gate arrays (FPGAs)-based embedded systems are easy to implement, reconfigure, test, and validate. Configurable logic blocks (CLBs) and memory blocks are the building blocks of FPGA. The rising issues in CMOS fabrication at smaller nanometer levels has increased the need for beyond-CMOS technologies to build complex circuits at extremely smaller nanometer levels. Quantum-dot cellular automata (QCA) is a nascent beyond-CMOS nanotechnology technique to design low-power and high-performance digital circuits. In this letter, a layout strategy is proposed to design QCA circuits. Using the proposed strategy, novel and cost-efficient designs of CLBs and memory blocks are proposed. The proposed blocks can be used to develop FPGA architecture and FPGA-based embedded systems in QCA. The proposed circuits are cost effective and perform better than many state-of-the-art designs. Simulation and verification are done in QCADesigner using coherence vector simulation engine.

A real-time FPGA accelerated stream processing for hyperspectral image classification

Realizing real-time classification of hyperspectral imagery has attracted researchers across various scientific and engineering disciplines. Several time-critical applications of high-resolution hyperspectral imaging require analysis of hyperspectral imagery with minimal turnaround time. In this regard, field-programmable gate arrays (FPGAs) provide cost-effective performance over the other high-performance reconfigurable computing systems. Developing such efficient systems poses several technical challenges such as designing and validating the FPGA architecture. A rapid prototyping approach offers several benefits in designing and developing FPGA architectures. This paper proposes a rapid prototyping method for the design and implementation of a multi-class support vector machine (MSVM) algorithm for real-time hyperspectral imagery classification using a low-cost FPGA system. We have evaluated design performance in terms of overall accuracy, resource utilization as well as timing requirements using four different datasets containing airborne, drone, and ground-based hyperspectral imagery. Experimental results show that the proposed FPGA design performs classification under strict real-time constraints.

Low power DNA protein sequence alignment using FSM state transition controller

In this paper we proposed an efficient computation technique for DNA patterns on reconfigurable hardware (FPGAs) platform. The paper also presents the results of a comparative study between existing dynamic and heuristic programming methods of the widely-used Smith-Waterman pair-wise sequence alignment algorithm with FSM-based core implementation. Traditional software implication-based sequence alignment methods can not meet the actual data rate requirements. Hardware-based approach will give high scalability and one can process parallel tasks with a large number of new databases. This paper explains finite state machine (FSM)-based core processing element to classify the protein sequence. In addition, we analyse the performance of bit-based sequence alignment algorithms and present the inner stage pipelined field programmable gate array (FPGA) architecture for sequence alignment implementations. Here, synchronised controllers are used to carry out parallel sequence alignment. The complete architecture is designed to carry out parallel processing in hardware, with FSM-based bit wised pattern comparison with scalability as well as with a minimum number of computations. Finally, the proposed design proved to be high performance and its efficiency in terms of resource utilisation is proved on FPGA implementation.

CSL: FPGA Implementation of Lightweight Block Cipher for Power-constrained devices

The exploration of interconnected devices, embedded devices, sensors, and various network-connected devices helps to communicate each other and exchange communications. These devices overcome with security threats related to privacy and data exchange over billions of devices are interconnected. Lightweight block ciphers aim to provide a feasible solution for power-constrained devices which includes Radio-frequency identification (RFID) tags, ubiquitous computing, wireless sensor network, aggregation network and IoT. In this paper, we have implemented a lightweight block cipher compact, secure, and lightweight (CSL). It operates on 64-bit block size, and key size varies from 64-bit to 128-bit key for encryption and decryption. The hardware implementation of CSL algorithm was thrived using field programmable gate array (FPGA) architecture. A pipelined design of compact S-boxes implemented on Digilent Nexys 4 DDR Artix™-7 board. Our experimental results of CSL consumes 1145 LUTs (Lookup Tables) and has fewer memory requirements. CSL shows resistant against various cryptanalytic attacks.

Implementation and optimisation of pulse compression algorithm on open CL‐based FPGA

As Moore's law meets bottlenecks, the demand for heterogeneous parallel processing systems is increasing. Field-programmable gate arrays (FPGAs) are becoming more efficient acceleration devices due to their powerful processing performance, and the CPU + FPGA architecture under the OpenCL framework has become the trend of heterogeneous parallel processing systems. This study focuses on the optimisation of pulse compression algorithm in FPGA based on OpenCL, which plays an important role in modern radar signal processing systems. By using double cache for ping–pang storage of data between matched filter and inverse fast Fourier transform (IFFT), an optimised processing method is proposed by using a pipeline and verify the method by using Arria 10 GX1150 FPGA with two groups of 2 GB DDR3; the results show that the proposed method can achieve 2.89× performance improvement over the conventional implementation.

Application-Dependent Testing of FPGA Interconnect Network

The extensive application of field-programmable gate array (FPGA) devices in industrial environments makes FPGA testing a significant area of exploration. The application-dependent testing approach ensures better manufacturing yield compared to the manufacturing testing process since it can bypass the faulty parts without disturbing a given user-defined design. The interconnection resources occupy a large area in the FPGA die, and it is highly error-prone due to the presence of a huge number of transistors. Interconnection resources testing play a major role in the reconfigurable hardware testing area. This paper presents an application-dependent testing technique to generate test configurations for interconnects in static RAM (SRAM)-based FPGAs. To generate a test pattern for interconnects, logic block configurations have been modified. This paper addresses stuck-at faults, different types of dominant bridging faults, and feedback bridging faults. Appropriate constraints have been designed using Boolean satisfiability to test the above faults in the interconnects. Simulations performed on ISCAS’89, MCNC, and ITC’99 benchmark circuits mapped on different FPGA architectures show that the proposed approach can obtain a minimum number of test configurations with 100% fault coverage for the above-mentioned faults and is technology independent which enables it to address new emerging architectures in FPGAs.

Combined weightless neural network FPGA architecture for deforestation surveillance and visual navigation of UAVs

This work presents a combined weightless neural network architecture for deforestation surveillance and visual navigation of Unmanned Aerial Vehicles (UAVs). Binary images, which are required for position estimation and UAV navigation, are provided by the deforestation surveillance circuit. Learned models are evaluated in a real UAV flight over a green countryside area, while deforestation surveillance is assessed with an Amazon forest benchmarking image data. Small utilization percentage of Field Programmable Gate Arrays (FPGAs) allows for a higher degree of parallelization and block processing of larger regions of input images.

Efficient separable convolution using field programmable gate arrays

Two-dimensional (2D) convolution is an essential component in several image and video processing applications. The convolution operation is computationally expensive due to the large number of required additions and multiplications. Field Programmable Gate Array (FPGA) architectures have been used to mitigate this problem owing to their parallel processing capabilities. Using separable filter kernels can further improve the convolution operation both in terms of resource utilization and speed. Although several 2D convolution implementations have been presented in the literature, research on separable convolution using FPGA is limited.This paper presents a new separable FPGA-based convolution architecture. The goal is to reduce both on-chip resource utilization and external memory bandwidth for a given processing rate of the convolution unit. External memory bandwidth (EMB) and on-chip resource utilization are reduced by reusing common data shared by consecutive processing windows in a novel way. Comparisons with existing separable convolution methods demonstrate improvements offered by the proposed technique in terms of on-chip resource utilization and power consumption.

FPGA-Based Stochastic Activity Networks for Online Reliability Monitoring

Stochastic activity network (SAN) is a flexible formalism that permits performing reliability and prognostics analysis of complex degrading systems. However, their use for the analysis of high-reliability equipment including fast evolving and degrading mechanisms requires long simulation times and large hardware resources. This paper presents, a field programmable gate array (FPGA)-based architecture that permits performing online Monte Carlo simulations of SAN models of high reliability systems. The synthesis is automated and the result preserves the structure of the models, permitting model inspection, and validation. The architecture runs without the aid of a central processing unit (CPU) and the simulation results are directly recorded into CPU-accessible random access memory (RAM). The design is validated on reliability monitors for an overheating detector and for degrading underground cables. The resource usage and simulation time are compared to the performance of software solutions that are run on parallel processors and large computer resources. Obtained results confirm that the proposed FPGA architecture can be employed for the accelerated runtime reliability analysis of equipment.

Hilbert filter based FPGA architecture for power quality monitoring

Power quality (PQ) related studies have become more relevant in recent years since the advent of modern industry related processes and technologies. As a result, PQ strategies have been formulated, facilitating a more efficient control in the generation and distribution of energy resources, therefore reducing both the operational cost for the provider, as well as the service fee for the consumer. This project develops a Hilbert Filter based methodology to monitor power quality indicators, through the analysis of voltage signals in order to detect disturbances that cause instability, quality drops or interruptions. The proposed methodology is implemented online, using digital signal processing based on field programmable gate arrays (FPGAs). As a result, a novel and simple methodology that detects the most common and important voltage disturbances for monitoring PQ is presented, as well as a discussion on its performance when compared to other current software-based alternatives available on the field.

Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit

DOI: 10.26650/electrica.2019.18052 Arithmetic Logic Unit (ALU) is the essential part of the Central Processing Unit (CPU) core which performs arithmetical operations such as addition, subtraction, division, multiplication etc., logical operations such as and, or, xor etc. and shift-rotate operations. The CPU performance is directly related to the performance of ALU. In this study, the 64-bit ALU has been designed by using the Very High Speed Integrated Circuits Hardware Description Language (VHDL) and Altera Field Programmable Gate Array (FPGA) families, synthesized and simulated with the help of Altera Quartus II (Intel, Santa Clara, CA, USA) v13.0sp1 and Modelsim-Altera v10.1d (Intel, Santa Clara, CA, USA) software. Many different studies are given about ALU Design and Implementation with the use of FPGA architecture and VHDL language. The difference of this study from recent studies is that the proposed design allows the processing of the signed numbers. Also, Conditional Sum Adder (COSA) is used in addition operation instead of Carry Ripple Adder (CRA) or Carry Look-ahead Adder (CLA) because of its benefit in fast addition and less propagation delay of Carry Chain. Cite this article as : Saglam Bedir N, Kacar F. Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit. Electrica 2019; 10.26650/electrica.2019.18052.

New Time-Domain Approach for Digital Signal Processing: A Set of Experimental Measures for Systems with High Transmission Rates

The essential purpose of this paper is to introduce to the current literature a new theoretical approach on how to implement the process of encoding data using a unique treatment with respect to the digital signal processing. Some relationships between a set of digital pulses and a special class of real polynomials allow us to identify the generation of a single pulse with an intrinsic dependence on the zero values of an arbitrary equation represented by a polynomial equation, where this direct match is established through an analytic operator. By using an ordinary field-programmable gate array architecture, it is possible to validate our theoretical approach, and we are presenting some experimental measurements, as well as one application on how to build a commercial data compressor for fiber optics. The algorithm here introduced presents an innovative technique, and its performance is faster per comparison. Furthermore, thanks to the math-to-time-domain transformations, it tends to overcome the current time required to process polynomial equations, which are involved in the data compression and data encryption systems.