An Efficient Implementation of Divergence State Estimation with Biogeography-Based Optimization (DSEBBO) Framework in FPGA-Based Multiprocessor System

Abstract

In recent years, Field Programmable Gate Array (FPGA) has different, and novel combinations of soft and hard cores embedded with accelerators in the same chip. At present, “Heterogeneous Multiprocessor System-on-Chip” technology meets the needs of the FPGA architecture as it not only consumes less space but also its design is implemented to enhance the performance resulting in decreased power consumption. However, traditional approaches can work within a limited range of values incurring high-power consumption, and they need substantial hardware resources involving complex procedures. In our proposed work, the combination of Graph Theory Estimator and Divergence State Estimation with Biogeography-Based Optimization (DSEBBO) is introduced. The principle notion of this proposed scheme is to optimize the required area resources and power consumption of the overall architecture by exploring the design space in a minimal time. The architecture uses a less number of hardware resources with a better outcome. The performances such as the latency, power consumption, delay, area and data rate are achieved better than the traditional works, and it is also application-aware with a multitask system. While comparing the outcome with the conventional asymmetric heterogeneous MPSoC method, the new DSEBBO design exhibits the performance improvement of 26.87% in data rate, and 37.18% reduction in average power consumption and 63.61% reduction in delay analysis under various traffic scenarios.