Abstract
Demanded by ever-evolving data processing algorithms, field-programmable gate arrays (FPGAs) have become essential components of modern computing systems, thanks to their reconfigurable and distributed computing capabilities. However, FPGAs are among the very few integrated chips that still require long development cycles and high human efforts, even for industrial vendors. In this article, we introduce OpenFPGA, an open-source framework that can automate and significantly accelerate the development cycle of customizable FPGA architectures. OpenFPGA allows users to customize their FPGA architectures down to circuit-level details using a high-level architecture description language and autogenerate associated Verilog netlists which can be used in a backend flow to generate production-ready layouts. A generic Verilog-to-Bitstream generator is also provided, allowing end-users to implement practical applications on any FPGAs that OpenFPGA can support. Using OpenFPGA, we demonstrate less than 24-h layout generation of two FPGA fabrics, which are based on a Stratix-like architecture built with a commercial 12-nm standard cell library and 40-nm custom cells, respectively.
Highlights
Demanded by ever-evolving data processing algorithms, field-programmable gate arrays (FPGAs) have become essential components of modern computing systems, thanks to their reconfigurable and distributed computing capabilities
Using OpenFPGA, standard cell FPGAs can be ported to advanced technology nodes with few manual efforts and benefit significant performance improvement
These works share the same principle with the production flow of the OpenFPGA framework, as depicted in Figure 1(a), where complete layout generation is achieved in two steps: 1) describe an FPGA architecture as Verilog netlists and 2) use commercial ASIC design tools to synthesize RTL designs into standard cell libraries
Summary
Previous works have proven the feasibility of agile production for customized FPGA fabrics by exploiting semicustom design flows.[3,4,5,6,7,8] These works share the same principle with the production flow of the OpenFPGA framework, as depicted in Figure 1(a), where complete layout generation is achieved in two steps: 1) describe an FPGA architecture as Verilog netlists and 2) use commercial ASIC design tools to synthesize RTL designs into standard cell libraries. Note that FPGA-Verilog and FPGA-bitstream generators are the core engines of the OpenFPGA frametom designed FPGAs have a customizable FPGA work, driving two types of design considerable performance gap when compared to commercial products This is mainly due fabrics and implement applications on the FPGAs. flows: (a) the production flow, which aims at achieving production-ready GDSII from an XML-based FPGA archito missing many pragmatic tecture description file; (b) the endfeatures of modern FPGAs. 1) Multimode logic blocks, which can effectively improve resource utilization rate, are only supported in recent works.[5,6]. FPGA-Bitstream is a generic bitstream generator, natively supporting any FPGA architecture that can be modeled by VPR as well as various circuit designs, such as fracturable LUTs, one/multilevel multiplexers, etc This indicates that instant EDA support for the FPGA fabric is ready for users once the XML-based architecture description is finalized. More details are available in the work by Tang et al.[11]
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