CSL: FPGA Implementation of Lightweight Block Cipher for Power-constrained devices

Abstract

The exploration of interconnected devices, embedded devices, sensors, and various network-connected devices helps to communicate each other and exchange communications. These devices overcome with security threats related to privacy and data exchange over billions of devices are interconnected. Lightweight block ciphers aim to provide a feasible solution for power-constrained devices which includes Radio-frequency identification (RFID) tags, ubiquitous computing, wireless sensor network, aggregation network and IoT. In this paper, we have implemented a lightweight block cipher compact, secure, and lightweight (CSL). It operates on 64-bit block size, and key size varies from 64-bit to 128-bit key for encryption and decryption. The hardware implementation of CSL algorithm was thrived using field programmable gate array (FPGA) architecture. A pipelined design of compact S-boxes implemented on Digilent Nexys 4 DDR Artix™-7 board. Our experimental results of CSL consumes 1145 LUTs (Lookup Tables) and has fewer memory requirements. CSL shows resistant against various cryptanalytic attacks.