A Novel Hybrid FPGA Architecture

Abstract

In this paper, a new hybrid field programmable gate array (FPGA) architecture is proposed. The logic tile, which consists of a logic cluster and related connection boxes (CBs), can be configured as either programmable logic arrays (PLAs) or look-up tables (LUTs). This architecture can be classified as AND-LUT array. PLAs are suitable for the implementation of large fan-in logic circuits, while LUTs are used to implement low fan-in logic circuits. As a result, the proposed hybrid FPGA architecture (HFA) is more flexible to improve logic density. Experimental results based on MCNC benchmark circuits were performed between the hybrid architecture and conventional LUT-based symmetrical FPGA architecture in term of area consumption. Preliminary results indicate that 46% chip area is reduced using the new architecture