Efficient separable convolution using field programmable gate arrays

Abstract

Two-dimensional (2D) convolution is an essential component in several image and video processing applications. The convolution operation is computationally expensive due to the large number of required additions and multiplications. Field Programmable Gate Array (FPGA) architectures have been used to mitigate this problem owing to their parallel processing capabilities. Using separable filter kernels can further improve the convolution operation both in terms of resource utilization and speed. Although several 2D convolution implementations have been presented in the literature, research on separable convolution using FPGA is limited.This paper presents a new separable FPGA-based convolution architecture. The goal is to reduce both on-chip resource utilization and external memory bandwidth for a given processing rate of the convolution unit. External memory bandwidth (EMB) and on-chip resource utilization are reduced by reusing common data shared by consecutive processing windows in a novel way. Comparisons with existing separable convolution methods demonstrate improvements offered by the proposed technique in terms of on-chip resource utilization and power consumption.