Field-effect Transistor Structure Research Articles

High-Frequency Performance Characteristics of the Double-Gate Schottky Barrier Tunnel Field Effect Transistor in Analog and Radio-Frequency Applications

In this paper, a novel structure of Double Gate Schottky Barrier Tunnel Field Effect Transistor (DG-SBTFET) has been designed and simulated. The DG-SBTFET has two sources (NiSi) and two gate metals with an HfO2. Silvaco-TCAD simulator has been used for investigating the analog and radio frequency performance of the DG-SBTFET. The proposed device (DG-SBTFET) is compared with the conventional devices in terms of electrical parameters including ION current, ION/IOFF ratio, RF performance including transconductances (gm), cut-off frequency (f T ), transit time (r), gain bandwidth product (GBP), transconductance generation factor (TGF), and transconductance frequency product (TFP). Further, we simulate the linearity characteristics of the DG-SBTFET device is compared it with other conventional devices, including the second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), and third-order input intercept point (IIP3). Hence, the proposed device (DG- SBTFET) is suitable for low-power and high-frequency applications.

Fabrication and Characterization of Self-Aligned WSe2 p-Type Field-Effect Transistor

Semiconducting transition metal dichalcogenides (TMDCs) have been growing interests as channel materials in field effect transistors (FET) for next generation low power digital electronics. [1]. Since a complementary metal oxide-semiconductor (CMOS) inverter constructed from pairs of n-type and p-type FETs is a fundamental building blocks in modern digital electronics [2], implementation of both n-type and p-type FETs with semiconducting TMDCs is of particular importance [3]. Among various semiconducting TMDCs, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [4]. These prominent features of WSe2 is suitable for an application to CMOS inverter.One of the significant challenges is to develop a top gate and top contact FET structure with WSe2 for CMOS device integration on the same wafer. In addition, it is desirable to minimize the access region between channel and S/D contact because this access region served as a series resistance to channel resistance, resulting in the lower drain current in FET. This study reports a self-aligned process to fabricate top gate and top contact WSe2 p-type FET. In this self-aligned structure, the gate electrode and source/drain contact edges are automatically positioned and hence there are no overlap or access region between the gate and source/drain. The feature of this proposed method is that the gate stacks was utilized as a mask for self-aligned formation of WOx, which is source/drain contact for efficient hole injection [5]. The focus on this study is the impact of self-aligned structure of p-type WSe2 FET on the electrical characteristics. The effectiveness of proposed process was experimentally demonstrated by the fabrication and characterization of device.Figures 1 shows the self-aligned fabrication process of p-type WSe2 FET. 20 nm-thick SiO2 was formed by dry oxidation of p+-Si substrate. The mechanically exfoliated multi-layer WSe2 was transferred by PDMS stamp. Next, 15 nm-thick Al2O3 was prepared by ALD at 200 oC with H2O. Then, Nickel (Ni) metal was deposited by RF sputtering on Al2O3. Ni metal was patterned for gate electrode with conventional lithography process. After that, A2O3 layer was removed by wet etching. Subsequently, substrate was exposed to oxygen radicals to form WOx used as source/drain contact at surface of WSe2. Second layer of Al2O3 was deposited as an encapsulating passivation layer. After the contact hole opening, the electrical contact pad was fabricated. Finally, forming gas (N2 : H2 = 97 % : 3 %) annealing was performed at 200 oC for 30 min. The top gate length was 5 μm. The gate width was estimated to be 40 μm by optical microscope. The electrical characteristics were measured with a manual probe station in an atmospheric pressure without inert gas purge at room temperature using a precision semiconductor parameter analyzer (Agilent 4156 C).Figures 2 shows the Id–Vg characteristics of fabricated FETs for (a) back gate operation and (b) top gate operation. Representative Id–Vg characteristics of p-type FETs were observed irrespective of back gate and top gate operation. The on/off ratio of about 106 ~ 107 order were obtained for both back gate and top gate operation. Furthermore, the threshold voltage and sub-threshold slope were modulated by varying the substrate bias during gate sweep.This study opens up interesting directions for the research and development of TMDC-based devices.AcknowledgmentsThis study was supported by a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616), a research grant for Tokyo Tech Challenging Research Award, the Samco Foundation and a research grant for Suematsu Award.

Electrical properties of a low-temperature fabricated Ge-based top-gate MOSFET structure with epitaxial ferromagnetic Heusler-alloy Schottky-tunnel source and drain

We show electrical properties of a Ge-based top-gate metal-oxide-semiconductor field-effect transistor (MOSFET) structure with epitaxial ferromagnetic Heusler alloy/Ge Schottky-tunnel contacts, fabricated with a low-temperature gate-stack process. For shaping the Ge-MOSFET with the ferromagnetic source and drain (S/D) contacts, we use a combination process of Ar+ ion milling and reactive ion etching (RIE). As a consequence of the formation of a gate stack (SiO2/GeO2) using a process temperature of 240 °C, we demonstrate inversion channel MOSFETs with a low gate-voltage operation (VG ∼5 V). Furthermore, we achieve a relatively high field-effect mobility (μFE) of ∼300 cm2/Vs compared to those in a Si-based back-gate spin-MOSFET reported previously [Phys. Rev. B 102, 035305 (2020).]. This study will open a way for developing a Ge-based top-gate spin-MOSFET on the Si platform.

Phase Transition Field Effect Transistor Observed in an α-(BEDT-TTF)2I3 Single Crystal

The metal–insulator transition induced by the gate electric field in the charge order phase of the α-(BEDT-TTF)2I3 single-crystal field-effect transistor (FET) structure was clearly observed near the phase transition temperature. An abrupt increase in the electrical conductance induced by the applied gate electric field was evident, which corresponds to the partial dissolution of the charge order phase triggered by the gate electric field. The estimated nominal dissolved charge order region (i.e., the gate-induced metallic region) was overestimated in 130–150 K, suggesting additional effects such as Joule heating. On the other hand, in the lower temperature region below 120 K, the corresponding dissolved charge order was several monolayers of BEDT-TTF, suggesting that it is possible to dissolve the charge order phase within the bistable temperature region.

Comparison of Carrier Deflection between MAG-TFET and MAG-FinFET

This paper is a comparison of the carrier deflection mechanism of a new magnetic sensor structure between the tunneling Field Effect Transistor (TFET) structure and the FinFET structures so-called MAG-TFET and MAG-FinFET.The device relies on carrier deflection from magnetically induced forces. The MAG-TFET current is caused by electron tunneling and drifting through the bulk under gate while the MAG-FinFET current is caused by the drift channel carrier from the inversion layer induced by gate voltages and there is also a bulk current beneath the substrate. The carrier deflection of the device is due to the current in the induced channel and current in the bulk. From the results, carrier deflection in the induced channel is better than in the bulk. The device sensitivity depends on the proportion of these two currents.

Minority carrier diffusion length in interface-confined PbS colloidal quantum dot (CQD): Effect of CQD surface modification on diffusion length in ultrathin PbS CQD films

Photocurrent microscopy (PCM) is a versatile tool for probing charge carrier transport associated with energy band bending at an interface. For the first time, we report the ligand-dependent electronic properties of interface-confined colloidal quantum dots (CQDs) near a metal electrode and gate dielectric layers using ultrathin lead sulfide (PbS) CQD films embedded in field effect transistors (FETs). We have compared the minority carrier (electron) diffusion length (MCDL) of ultrathin PbS CQD films treated with 1,2-ethanedithiol (EDT) and ammonium sulfide ((NH4)2S) using a bottom-contact FET structure in combination with PCM. We found that the MCDL was greater in the EDT-treated PbS CQDs than in the (NH4)2S-treated PbS CQDs. The MCDL at the 2D carrier accumulation layer was observed to depend on the concentration of the majority carrier (hole). During effective electrical channel formation by electrical gating, the MCDL decreased with hole accumulation (decreasing gate voltage) in the p-channel (NH4)2S-treated PbS CQD FET, whereas it remained similar in the EDT-treated PbS CQD FET. The effect of the majority carrier concentration on the MCDL was more pronounced in the (NH4)2S-treated sample than in the EDT-treated sample. The difference in the MCDL is attributed to a difference in the surface trap density caused by different ligand treatments.

Single silicon synaptic device for stochastic binary spike-timing-dependent plasticity

In this paper, we present a single silicon synaptic device that enables stochastic binary spike-timing-dependent plasticity. The single silicon synaptic device, which is similar to a conventional metal-oxide-semiconductor field-effect transistor structure, is implemented using standard complementary metal-oxide-semiconductor technology. The stochastic nature of the feedback mechanism induced by weak impact ionization is experimentally demonstrated. Because of probabilistic dynamics in the feedback mechanism, the single silicon synaptic device features stochastic binary spike-timing-dependent plasticity.

Complementary Doped Source-Based Reconfigurable Schottky Diode as an Equivalence Logic Gate.

A complementary doped source-based reconfigurable Schottky diode (CDS-RSD) is proposed for the first time. Unlike other types of reconfigurable devices that have source and drain (S/D) regions with the same material, this has a complementary doped source region as well as a metal silicide drain region. Compared to three-terminal reconfigurable transistors, which have both the program gate and control gate, the proposed CDS-RSD does not have a control gate but only a program gate for reconfiguration operation. The drain electrode of the CDS-RSD is not only the output terminal of the current signal but also the input terminal of the voltage signal. Therefore, it is a reconfigurable diode based on high Schottky barriers for both the conduction band and valence band of silicon, which formed on the interface between the silicon and drain electrode. Therefore, the CDS-RSD can be regarded as the simplification of the reconfigurable field effect transistor structure on the premise of retaining the reconfigurable function. The simplified CDS-RSD is more suitable for the improvement of logic gate circuit integration. A brief manufacture process is also proposed. The device performance has been verified through device simulation. The performance of the CDS-RSD as a single-device two-input equivalence logic gate has also been investigated.

Three-Dimensional MoS2 Nanosheet Structures: CVD Synthesis, Characterization, and Electrical Properties

The proposed study demonstrates a single-step CVD method for synthesizing three-dimensional vertical MoS2 nanosheets. The postulated synthesizing approach employs a temperature ramp with a continuous N2 gas flow during the deposition process. The distinctive signals of MoS2 were revealed via Raman spectroscopy study, and the substantial frequency difference in the characteristic signals supported the bulk nature of the synthesized material. Additionally, XRD measurements sustained the material’s crystallinity and its 2H-MoS2 nature. The FIB cross-sectional analysis provided information on the origin and evolution of the vertical MoS2 structures and their growth mechanisms. The strain energy produced by the compression between MoS2 islands is assumed to primarily drive the formation of vertical MoS2 nanosheets. In addition, vertical MoS2 structures that emerge from micro fissures (cracks) on individual MoS2 islands were observed and examined. For the evaluation of electrical properties, field-effect transistor structures were fabricated on the synthesized material employing standard semiconductor technology. The lateral back-gated field-effect transistors fabricated on the synthesized material showed an n-type behavior with field-effect mobility of 1.46 cm2 V−1 s−1 and an estimated carrier concentration of 4.5 × 1012 cm−2. Furthermore, the effects of a back-gate voltage bias and channel dimensions on the hysteresis effect of FET devices were investigated and quantified.

Carrier Transport Properties in Few-Layer WS0.3Se1.7/(WOx)WS0.3Se1.7 Lateral p+–n Junctions Using a Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) Structure

The carrier transport properties of lateral p+–n junctions composed of few-layer WS0.3Se1.7/(WOx)WS0.3Se1.7 on thermally grown SiO2 or high-κ amorphous Al0.74Ti0.26Oy dielectric layers on p+-Si substrates were investigated and analyzed using field-effect transistor structures. Plasma-laser irradiation promoted selective oxidation near the few-layer WS0.3Se1.7 surface and improved the rectification behavior of the current–voltage characteristics. A photocurrent current density (Jph) of 4 × 10–7 A/cm2 was recorded for WS0.3Se1.7/(WOx)WS0.3Se1.7 lateral p+–n junctions under simulated solar-light (AM1.5G) irradiation. Subsequently, improved Jph values of 7.1 × 10–6 (∼17 times) and 1.23 × 10–5 A/cm2 (∼30 times) were obtained by inserting a silver (Ag) back-reflector layer between the amorphous Al0.74Ti0.26Oy dielectric layer and p+-Si and an adding an antireflection (AR) layer of SnO2, respectively. In addition, an enhanced Jph of 1.3 × 10–5 A/cm2 was achieved with a Voc of 0.84 V and an FF of 57% upon applying a gate bias of +12 V. Thus, the photonic and electronic design of lateral p+–n junctions composed of few-layer WS0.3Se1.7/(WOx)WS0.3Se1.7 structures contributes to further research on various types of 2D lateral heterostructures for the application in optoelectronic and photovoltaic devices.

Performance investigation of a charge plasma tunnel FET with SiGe source pocket as a photosensor

This study investigates a highly sensitive and low-power photosensor using a pocket-based charge plasma tunnel field-effect transistor (PCPTFET) structure for visible light detection. Here, zinc oxide, the transparent optical region over the channel, is the catalyst for the photo-sensing operation. When light strikes the sensitive portion of the device, creating optical charge carriers in the illumination region and substantially increases the device’s conductance. The analysis of various parametric and structural variations like intensity power density (Pj ), optical wavelength (λ), drain to source voltage (V DS), incident angle (θ), and silicon body thickness (t si) have been investigated for the reported pocket-based charge plasma TFET (PCPTFET) photosensor. Further, the PCPTFET’s superior performance as a highly sensitive photosensor is revealed by comparing the several optical figures of merit (FOM) with conventional tunnel field-effect transistor. The reported photosensor provides much-improved responsivity (R) of 1.52 A W−1 and quantum efficiency (η) of 4.96.

MOCVD-grown β-Ga2O3 as a Gate Dielectric on AlGaN/GaN-Based Heterojunction Field Effect Transistor

We report the electrical properties of Al0.3Ga0.7N/GaN heterojunction field effect transistor (HFET) structures with a Ga2O3 passivation layer grown by metal–organic chemical vapor deposition (MOCVD). In this study, three different thicknesses of β-Ga2O3 dielectric layers were grown on Al0.3Ga0.7N/GaN structures leading to metal-oxide-semiconductor-HFET or MOSHFET structures. X-ray diffraction (XRD) showed the (2¯01) orientation peaks of β-Ga2O3 in the device structure. The van der Pauw and Hall measurements yield the electron density of ~ 4 × 1018 cm−3 and mobility of ~770 cm2V−1s−1 in the 2-dimensional electron gas (2DEG) channel at room temperature. Capacitance–voltage (C-V) measurement for the on-state 2DEG density for the MOSHFET structure was found to be of the order of ~1.5 × 1013 cm−2. The thickness of the Ga2O3 layer was inversely related to the threshold voltage and the on-state capacitance. The interface charge density between the oxide and Al0.3Ga0.7N barrier layer was found to be of the order of ~1012 cm2eV−1. A significant reduction in leakage current from ~10−4 A/cm2 for HFET to ~10−6 A/cm2 for MOSHFET was observed well beyond pinch-off in the off-stage at -20 V applied gate voltage. The annealing at 900° C of the MOSHFET structures revealed that the Ga2O3 layer was thermally stable at high temperatures resulting in insignificant threshold voltage shifts for annealed samples with respect to as-deposited (unannealed) structures. Our results show that the MOCVD-gown Ga2O3 dielectric layers can be a strong candidate for stable high-power devices.

Manipulating the magnetic and electric transport properties of La0.7Sr0.3MnO3 epitaxial thin film through ionic liquid-gated technology

Reversible manipulation of magnetic and electric transport properties by electrical means in perovskite transition metal oxides is of paramount importance in modern condensed matter physics and generates promising application prospects in electronic devices. However, the conventional method of field-effect transistor structure presents a huge limitation due to its poor ability to modulate the exceedingly high carrier density of about 1014−1015 cm−2. In this study, La0.7Sr0.3MnO3 (LSMO) epitaxial thin films with tensile and compressive strain states were obtained by growth on different single-crystal substrates. Compared with the LSMO thin film under tensile strain, the compressed LSMO thin film possesses more oxygen vacancies, a higher resistance and a smaller magnetization. In addition, the structural phases, magnetic and electric transport properties in both LSMO thin films were also manipulated by the ionic liquid-gated method. The LSMO thin film under compressive strain shows easier access to the reversible control of the structural phase and magnetic & electrical transport properties than the LSMO thin film under tensile strain. The synergy of the above capabilities proves an effective and reversible route to manipulate the properties of perovskite transition metal oxides, providing tremendous potential in the design of multiple-state memories, neuromorphic transistors, and other multifunctional devices.

Bulk-fin field-effect transistor-based capacitorless dynamic random-access memory and its immunity to the work-function variation effect

In this study, we developed a capacitorless dynamic random-access memory (DRAM) (1T-DRAM) device based on a junctionless (JL) bulk-fin field-effect transistor structure with excellent reliability and negligible variability against work-function variation (WFV). We investigated the variation in the transfer characteristics and memory performance of the memory cell owing to WFV. In particular, to investigate the WFV effect, we analyzed the transfer characteristics and memory performance of 200 samples using four metal-gate materials—TiN, MoN, TaN and WN. Consequently, we discovered that the WFV affected the transfer characteristics of the JL bulk-fin field-effect transistor. However, the proposed 1T-DRAM demonstrated that the sensing margin and retention time produced minimal effect owing to the adoption of a structure storing holes in the fin region. Consequently, the proposed 1T-DRAM exhibited strong WFV immunity and excellent reliability for memory applications.

Performance analysis of FinFET based inverter, NAND and NOR circuits at 10 NM,7 NM and 5 NM node technologies

Advancement in the semiconductor industry has transformed modern society. A miniaturization of a silicon transistor is continuing following Moore?s empirical law. The planar metal-oxide semiconductor field effect transistor (MOSFET) structure has reached its limit in terms of technological node reduction. To ensure the continuation of CMOS scaling and to overcome the Short Channel Effect (SCE) issues, a new MOS structure known as Fin field-effect transistor (FinFET) has been introduced and has led to significant performance enhancements. This paper presents a comparative study of CMOS gates designed with FinFET 10 nm, 7 nm and 5 nm technology nodes. Electrical parameters like the maximum switching current ION, the leakage current IOFF, and the performance ratio ION/IOFF for N and P FinFET with different nodes are presented in this simulation. The aim and the novelty of this paper is to extract the operating frequency for CMOS circuits using Quantum and Stress effects implemented in the Spice parameters on the latest Microwind software. The simulation results show a fitting with experimental data for FinFET N and P 10 nm strctures using quantum correction. Finally, we have demonstrate that FinFET 5 nm can reach a minimum time delay of td=1.4 ps for CMOS NOT gate and td=1 ps for CMOS NOR gate to improve Integrated Circuits IC.

A review on effect of various high-k dielectric materials on the performance of FinFET device

The scalability of bulk CMOS faced various possible issues due to inherent material and process innovation constraints. Alternatively, transistor devices with supplementary gates, such as the Fin Field-effect transistor (FinFET) structure has attracted developing interest during the last few generations of their emergence, attributable to the appropriate control of the gate electrode over subthreshold parameters and seem to be favorable for Ultra large-scale integration, resulting in excessive immune function to short-channel effects (SCEs). In this paper, we will see the effect of several types of high-k gate dielectrics materials i.e Hafnium oxide (HfO2), Lanthanum doped zirconium oxide (LaZrO2), Silicon dioxide (SiO2), crystalline-silicon (c-Si), and polycrystalline-silicon (poly-Si), etc. channels are characterized for the short channel effects (SCEs), leakage current, Ion/Ioff ratio, drain induced barrier lowering (DIBL), and subthreshold swing (SS). The effect of important device parameters is considered regarding SCEs. The variation of the materials indicates improvements for the SCEs in FinFETs device architecture and also enhanced effective carrier mobility. Hence, we can clearly see that the use of high-k gate material has allowed for effective control of the diminishing of short channel effects.

Qualitative Analysis of DG-TFET Structures with Gate Material Engineering

The paper largely focuses on enhancing device parameters of a Double Gate Tunnel Field Effect Transistor structure such as ON current, OFF Current,transconductance and ratio of ON current to OFF current (ION / IOFF) using hetero dielectric gate material. The paper presents three state of art of dual gate TFET i.e., Conventional Double Gate TFET (CDGTFET), horizontally placed Dual Material Double Gate TFET (HDMDGTFET), vertically placed Dual Material Double Gate TFET (VDMDGTFET). The dual material dielectric combinations used in the structures are (SiO2-TiO2), (HfO2-TiO2) and (SiO2-SiC). The Structures are being modeled using Silvaco Atlas tool. Simulations of these structures are carried out and various electrical parameters have been obtained. The results obtained from simulation of these structures are being presented and discussed in this paper. Comparison of the three structures is carried out and resulted in the reduction of ON Current and OFF Current is observed.

Fast and sensitive terahertz detection with a current-driven epitaxial-graphene asymmetric dual-grating-gate field-effect transistor structure

We designed and fabricated an epitaxial-graphene-channel field-effect transistor (EG-FET) featuring an asymmetric dual-grating-gate (ADGG) structure working as a current-driven terahertz detector and experimentally demonstrated a 10 ps-order fast response time and a high responsivity of 0.3 mA/W to 0.95 Terahertz (THz) radiation incidence at room temperature. The ADGG and drain–source bias dependencies of the measured photoresponse showed a clear transition between plasmonic detection under periodic electron density modulation conditions with depleted regions and photothermoelectric (PTE) detection under entirely highly doped conditions without depleted regions. We identified the PTE detection that we observed as a new type of unipolar mechanism in which only electrons or holes contribute to rectifying THz radiation under current-driven conditions. These two detection mechanisms coexisted over a certain wide transcendent range of the applied bias voltages. The temporal photoresponses of the plasmonic and PTE detections were clearly shown to be comparably fast on the order of 10 ps, whereas the maximal photoresponsivity of the PTE detection was almost twice as high as that of the plasmonic detection under applied bias conditions. These results suggest that the ADGG-EG-FET THz detector will be promising for use in 6G- and 7G-class high-speed wireless communication systems.

Photoelectron spectromicroscopy analysis of graphene during gate-controlled photo-oxidation process

The analysis of chemical reactions in two-dimensional (2D) materials is becoming increasingly important for device applications. Typically, 2D materials are in the form of small flakes; therefore, local inhomogeneities between or within the flakes should be investigated. In this study, we investigated the gate-controlled UV photo-oxidation reaction of monolayer graphene sheets using field-effect transistor structures. We performed a surface characterization of the photo-oxidized graphene micro-sheets using an original scanning photoelectron microscopy system that enables element-selective electronic and chemical state analysis with a high spatial resolution. We succeeded for the first time in experimentally revealing the progression of the photo-oxidation reaction in graphene from the edge. During the photo-oxidation process, hole doping from the adsorbed molecules occurred first. The reaction proceeded selectively to the edges of the graphene sheets. Defects were then introduced by chemical reactions with adsorbed molecules, and finally the graphene sheets decomposed and disappeared.

Investigation on the Negative Capacitance Field Effect Transistor with Dual Ferroelectric Region

This paper proposes a new structure of the negative capacitance field effect transistor (NCFET), which features of the dual ferroelectric region (DFR) when compared to the conventional NCFET. The dual ferroelectric region with FE1 region and FE2 region forms a non-uniform voltage amplification effect, leads to the significantly improvement of the gate control ability and modulates the electric characteristics of the NCFET. The mechanism of the voltage amplification effect, polarization reversal, channel surface electric field, and ferroelectric polarization intensity distributions are investigated. The influences of the ferroelectric parameters α and β on the electric characteristics are discussed. The results show that the DFR-NCFET is able to obtain a subthreshold swing (SS) below the Boltzmann limit (60 mV/dec) by increasing the ferroelectric parameter α of the FE2 region.