FDSOI MOSFETs Research Articles

Parasitic bipolar effect in ultra-thin FD SOI MOSFETs

The parasitic bipolar effect is investigated in fully-depleted silicon-on-insulator (FD SOI) n-type MOSFETs with ultra-thin films (5–10nm). Our measurements show that at low drain bias the drain leakage current is governed by the gate current. Beyond VD>1.0V, leakage current amplification is observed in short-channel 10-nm thick devices. With film thickness shrinking, the current amplification is suppressed. We explain this amplification by the turn-on of the lateral parasitic bipolar transistor. TCAD simulations confirm that the parasitic bipolar is activated due to holes generated by band-to-band tunneling at the drain side and accumulated in the floating body. An effective method for the extraction of bipolar gain is proposed based on the comparison of leakage current in short- and long-channel devices. The experimental method is validated through simulations.

Wide frequency band assessment of 28 nm FDSOI technology platform for analogue and RF applications

This work presents an in-depth wide-frequency band assessment of 28nm FDSOI MOSFETs for analogue and RF applications. The focus is mainly on such figures of merit (FoM) as the transconductance gm, the output conductance gd, the intrinsic gain Av and the cut-off frequencies fT and fmax. Firstly, 28nm FDSOI MOSFETs are compared with other advanced devices and are shown to outperform them. Secondly, gm–Av analogue metric is demonstrated to be affected by operation frequency. Small-signal parameters variation is limited and dominated by self-heating effect. This is in contrast to the first generation of ultra-thin body and BOX devices without a ground plane where coupling through the substrate has a considerable effect. Thirdly, the self-heating effect is analysed and shown to be smaller than previously predicted by simulations for such devices. Fourthly, it is shown that fT of ∼280GHz and fmax of ∼250GHz are reachable in the shortest devices. These values are compared to those of the first generation of UTBB devices through the effect of parasitic elements.

Extraction of the Parasitic Bipolar Gain Using the Back-Gate in Ultrathin FD SOI MOSFETs

We propose a new method to extract the gain of the parasitic bipolar transistor in ultrathin fully-depleted silicon-on-insulator MOSFETs. The method is based on the modulation of the parasitic bipolar effect by back-gate biasing. The bipolar gain can be determined for each transistor, without the need to compare the long and short devices. The proposed method is validated by experimental data and numerical simulations.

Designing and simulation SOI MOSFET transistorsto enhance DIBL parameterand improveself-thermal effects

Abstract. In this study, a new structure for FD SOI MOSFET has been presented toimprove DIBL parameter and also to enhance self-heating effect. The main idea of this structure is to change the thickness of BOX layer in transistor in order to improve DIBL parameter and self-heating effect.

Usage and Limitation of Standard Mobility Models for TCAD Simulation of Nanoscaled FD-SOI MOSFETs

TCAD tools have been largely improved in the last decades in order to support both process and device complementary simulations which are usually based on continuously developed models following the technology progress. In this paper, we compare between experimental and TCAD simulated results of two kinds of nanoscale devices: ultrathin body (UTB) and nanoscale Body (NSB) SOI-MOSFET devices, sharing the sameW/Lratio but having a channel thickness ratio of 10 : 1 (46 nm and 4.6 nm, resp.). The experimental transferI-Vcharacteristics were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a large gate voltage dependent series resistance (RSD). TCAD tools do not usually considerRSDto be either channel thickness or gate voltage dependent. After observing a clear discrepancy between the mobility values extracted from our measurements and those modeled by the available TCAD models, we propose a new semiempirical approach to model the transfer characteristics.

Overestimation of Short-Channel Effects Due to Intergate Coupling in Advanced FD-SOI MOSFETs

The short-channel effects (SCE) in advanced fully depleted silicon-on-insulator MOSFETs are investigated by showing the importance of the intergate coupling. Experimental results highlight that part of the SCE is due to the contribution of the opposite-gate, leading to systematic overestimation of the threshold voltage roll-off and drain-induced barrier lowering (DIBL) effects. Numerical simulations confirm that the impact of back-gate SCE depends on the device structure (film and oxide thickness) and bias. A basic model is presented, which enables the identification of the genuine SCE at each gate. To mitigate or fully cancel the threshold voltage roll-off and DIBL, we propose simple and pragmatic back-biasing schemes.

Effect of parasitic elements on UTBB FD SOI MOSFETs RF figures of merit

This work details the harmful effect of parasitic resistances and capacitances on RF figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) FD SOI n-MOSFETs. It is demonstrated that intrinsically, UTBB device can reach very high cut-off frequency (fT) provided the reduction of parasitic elements. In addition, based on device simulation, we demonstrate that with appropriate configuration, Asymmetric Double Gate (ADG) regime provides a slight improvement of RF figures-of-merit.

Impact of Single Charge Trapping on the Variability of Ultrascaled Planar and Trigate FDSOI MOSFETs: Experiment Versus Simulation

The impact of single charge trapping on the threshold voltage Vt of ultrascaled fully depleted silicon-on-insulator transistors is investigated through dynamic variability measurements and 3-D electrostatic simulations. In these undoped Si channel devices, Vt shifts induced by individual trapping events are exponentially distributed with distribution tail similarly as in BULK devices. This typical dependence is explained by the high sensitivity of Vt -with a bell-like shape-on the position of the trap over the channel. The tail, on the other hand, is attributed to defects in the buried oxide. Finally, device scaling is showed to increase dynamic Vt variability. In particular, the impact of a single charge on Vt is found to scale with the inverse of the device area.

Unusual Short-Channel Effects in SOI MOSFETs

Experimental results demonstrate that the usual interpretation of short-channel effects (SCE) is misleading in FD-SOI MOSFETs, where both gates contribute to SCE via inter-gate coupling. The overall SCE can be significantly reduced with simple back-gate biasing schemes. Numerical simulations point out that the contribution of the back channel to SCE strongly depends on the device architecture.

Modeling of low frequency noise in FD SOI MOSFETs

In this paper, we present the modeling of low frequency noise of FD SOI devices in the front and back interface channel operations. We present an analytical model for the inversion charge power spectral density in FD SOI MOSFETs. This analytical model is valid for the different modes of operation of the device, in both the front and the back conduction regimes. The simulation results are compared to those obtained using our numerical model presented in a previous work and to experimental data. A very good agreement between both models and the measurements is obtained. We show that when only the back channel is activated, the influence of the front oxide noise contribution can be neglected.

New parameter extraction method based on split C–V measurements in FDSOI MOSFETs

A new parameter extraction methodology based on split C–V is proposed for FDSOI MOS devices. To this end, a detailed capacitance theoretical analysis is first conducted emphasizing the usefulness of the Maserjian function. Split C–V measurements carried out on various FDSOI CMOS technologies show that the Maserjian function exhibits a power law dependence with inversion charge as ∝Qi−2 whatever the carrier type and gate oxide thickness. This feature enables to confirm the validity of a two-parameter simple capacitance model and allows for a reliable MOSFET parameter extraction in FDSOI devices.

Back-Gate Bias Dependence of the Statistical Variability of FDSOI MOSFETs With Thin BOX

The impact of back-gate bias on the statistical variability (SV) of FDSOI MOSFETs with thin buried oxide (BOX) is studied via 3-D “atomistic” drift-diffusion simulation. The impact of the principal sources of SV, i.e., random dopant fluctuations, line edge roughness, and metal gate granularity, on threshold voltage, drain-induced barrier lowering, and drive current is studied in detail. It is shown that reverse back-bias is beneficial in terms of reducing the dispersion of the off-current and the corresponding standby leakage power, whereas forward back-bias reduces the on -current variability. The correlation coefficients between relevant figures of merit and their trends against back-bias are also studied in detail, providing guidelines for the development of statistical compact models of thin-BOX FDSOI MOSFETs for low-standby-power circuit applications.

Revisited approach for the characterization of Gate Induced Drain Leakage

This work presents a critical review and a re-investigation of the electrical characterization of Gate Induced Drain Leakage (GIDL) [1,2]. The underlying assumptions of the previously proposed extraction methods are exposed and their ability to capture Band-to-Trap mechanisms is discussed. A new approach is introduced to overcome some of the limiting assumptions made by the previous extraction methods. This new approach is benchmarked against the previously proposed ones. The results show that it enables a better extraction of the GIDL parameters compared to the conventional methods, by using the voltage dependency of the activation energy to gain insight in the electric field responsible for Band-to-Band Tunneling in the device. Finally, the experimental application of this new approach is carried out on cold process FDSOI MOSFET and confirms the ability of this new method to quantify the impact of trap assisted tunneling on GIDL.

0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs

It is shown that it is feasible to apply 0.5-V 6-T SRAM cells in a 25-nm high-speed 1-Gb e-SRAM. In particular, for coping with rapidly reduced voltage margin as VDD is reduced, a boosted word-voltage scheme is first proposed. Second, Vt variations are reduced with repair techniques and nanoscale FD-MOSFETs to further widen the voltage margin. Third, a worst case design is developed, for the first time, to evaluate the cell. This design features a dynamic margin analysis and takes subthreshold current, temperature, and Vt variations and their combination in the cell into account. Fourth, the proposed scheme is evaluated by applying the worst-case design and a 25-nm planar FD-SOI MOSFET. It is consequently found that the scheme provides a wide margin and high speed even at 0.5V. A 0.5-V high-speed 25-nm 1-Gb SRAM is thus feasible. Finally, to further improve the scheme, it is shown that it is necessary to use FinFETs and suppress and compensate process, voltage, and temperature variations in a chip and wafer.

New numerical low frequency noise model for front and buried oxide trap density characterization in FDSOI MOSFETs

In this paper, we present a new numerical model of the inversion charge power spectral density in FDSOI MOSFET devices with ultra thin body. Numerical simulation results are compared to those of the classical formulation and to experimental data. A good agreement of measurements is obtained with the proposed model. The results show that the noise behavior in FDSOI MOSFETs is strongly related to the front and buried oxides defects, even if the channel is located at the front interface. In other words, the classical formulation of the flat-band voltage power spectral density (PSD) overestimate the front oxide trap density and no more holds true in SOI MOSFETs LFN characterization.

Performance Evaluation of FD-SOI MOSFETS for Different Metal Gate Work Function

Fully depleted (FD) Silicon on Insulator (SOI) metal oxide Field Effect Transistor (MOSFET) Is the Leading Contender for Sun 65nm Regime. This paper presents a study of effects of work functions of metal gate on the performance of FD-SOI MOSFET. Sentaurus TCAD simulation tool is used to investigate the effect of work function of gates ont he performance FDSOI MOSFET. Specific channel length of the device that had been concentrated is 25nm. From simulation we observed that by changing the work function of the metal gates of FD-SOI MOSFET we can change the threshold voltage. Hence by using this technique we can set the appropriate threshold voltage of FD-SOI MOSFET at same voltage and we can decrease the leakage current, gate tunneling current and short channel effects and increase drive current.

Study of Random Dopant Fluctuation Effects in FD-SOI MOSFET Using Analytical Threshold Voltage Model

An analytical threshold voltage model developed for a nonuniformly doped channel is used to study the random dopant fluctuation (RDF) effects in FD-SOI MOSFETs. RDF results in nonuniform doping in the channel, leading to deviation in the threshold voltage, which can be computed using this analytical model. The effect of device parameters on RDF-induced threshold voltage deviations is also investigated. For each study, a large sample size has been used. This has been possible owing to the computational efficiency of the analytical model. Studies on the threshold voltage variation due to combined effects of RDF and other device parameter fluctuations have also been carried out.

A Novel Step-Doping Fully-Depleted Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor for Reliable Deep Sub-micron Devices

For first time, we report a novel deep sub-micron fully-depleted silicon-on-insulator metal–oxide–semiconductor field-effect-transistor (FD SOI MOSFET) where the channel layer consists of two sections with a step doping (SD) region in order to increase performance and reliability of the device. This new structure that called SD FD SOI structure (SDFD-SOI MOSFET), were used for reaching suitable threshold voltage upon device scaling and reliability improvement. We demonstrate that the electric field was modified in the channel and common peak near the source junction have been reduced in the SDFD-SOI structure. The device demonstrates large enhancements in performance areas such as current drive capability, output resistance, hot-carrier reliability and threshold voltage roll-off. It was found that the device performance is very much dependent upon the SD region parameters. Simulation results show that the proposed structure improved on/off current ratio, and saturated output characteristics compared with conventional SOI structure (C-SOI MOSFET). Also, it was shown that substrate current of SDFD-SOI MOSFET is much lower than the C-SOI MOSFET which presented the lower hot-carrier degradation in proposed MOSFET. Results show that the most short-channel problems in very large scale integrated circuits (VLSI) could be solved and the proposed SDFD-SOI MOSFETs can work very well in deep sub-micron and nanoscale regime.

Experimental demonstration and analysis of high performance and low 1/f noise Tri-gate MOSFETs by optimizing device structure

In this paper, we experimentally investigate the performance of multi-gate MOSFETs (MUGFETs) using the advanced radical gate oxide and the accumulation-mode (AM) FD-SOI MOSFETs. Firstly, we experimentally demonstrate that the drain current in AM multi-gate MOSFET is improved about 1.3 times compared with conventional inversion-mode (IM) MOSFETs with the same gate oxide. Secondly, we indicate that 1/f noise levels in AM MUGFETs are obviously suppressed compared with the conventional IM MUGFETs. The advantages resulted from the AM device structure for MUGFETs are demonstrated in this experiment.

Specific features of multiple-gate MOSFET threshold voltage and subthreshold slope behavior at high temperatures

In this paper specific features of the multiple-gate MOSFETs (MuGFETs) behavior at high temperatures (up to 300 °C) are analyzed through measurements, 2D simulations and analytical models of long-channel transistors. The high-temperature evolutions of threshold voltage and subthreshold slope are discussed paying particular attention to the influence of Si film thinning. High-temperature behavior of the threshold voltage and subthreshold slope in MuGFETs is demonstrated, for the first time, to be different from those generally considered for FD SOI MOSFETs. It is shown that the threshold voltage shift with temperature is strongly attenuated in MuGFETs and further decreases with Si film thinning. Then, the deviation of the MuGFET subthreshold slope at high temperatures from the expected ideal linear temperature dependence is analyzed and the possible reasons are discussed.