Erase Speed Research Articles

Speed Enhancement of WSi2 Nanocrystal Memory with Barrier-Engineered Si3N4/HfAlO Tunnel Layer

WSi2 nanocrystal nanofloating gate capacitors with multistacked Si3N4/HfAlO high-k tunnel layers were fabricated and their electrical properties were characterized. The thicknesses of the Si3N4 and HfAlO tunnel layers were 1.5 and 3 nm, respectively. The asymmetrical Si3N4/HfAlO tunnel layer was modulated to enhance the tunneling efficiency to improve program and erase speeds. The flat-band voltage shift of the WSi2 nanofloating gate capacitor was about 7.2 V after applied voltages swept were from -10 to 10 V and from 10 to -10 V. Then, the program/erase speeds and the memory window under programming and erasing at ±7 V were 300 µs and 1 V, respectively. As demonstrated in the results, the WSi2 nanocrystal memory with barrier-engineered Si3N4/HfAlO layers could be applied to enhance the program and erase speeds at low operating voltages for nanocrystal nonvolatile memory application.

A New Recess Method for SA-STI nand Flash Memory

In this letter, we propose a new shallow trench isolation (STI) recess effect on the self-aligned STI of nand Flash memory devices. In the current nand Flash cell design, increasing the recess depth of STI recess yields a higher gate coupling ratio and lower floating-gate (FG) interference to achieve better immunity to process fluctuation. However, the current design is limited by significantly slower Fowler–Nordheim (FN) erase speed and degraded channel characteristics. Slow erase speed is caused by the accumulation of holes around channel edges, while the degraded channel is owing to FN cycling stress-induced interface damage. The proposed STI recess structure maintains a proper distance between the channel edge and the control gate, as well as blocks the FG interference without increasing cell-to-cell spacing.

산화막과 질화막 위에 제작된 3D SONOS 다층 구조 플래시 메모리소자의 1/f 잡음 특성 분석

In this paper, we compared and analyzed 3D silicon-oxide-nitride-oxide-silicon (SONOS) multi layer flash memory devices fabricated on nitride or oxide layer, respectively. The device fabricated on nitride layer has inferior electrical properties than that fabricated on oxide layer. However, the device on nitride layer has faster program / erase speed (P/E speed) than that on the oxide layer, although having inferior electrical performance. Afterwards, to find out the reason why the device on nitride has faster P/E speed, 1/f noise analysis of both devices is investigated. From gate bias dependance, both devices follow the mobility fluctuation model which results from the lattice scattering and defects in the channel layer. In addition, the device on nitride with better memory characteristics has higher normalized drain current noise power spectral density (<TEX>$S_{ID}/I^2_D$</TEX>>), which means that it has more traps and defects in the channel layer. The apparent hooge's noise parameter (<TEX>${\alpha}_{app}$</TEX>) to represent the grain boundary trap density and the height of grain boundary potential barrier is considered. The device on nitride has higher <TEX>${\alpha}_{app}$</TEX> values, which can be explained due to more grain boundary traps. Therefore, the reason why the devices on nitride and oxide have a different P/E speed can be explained due to the trapping/de-trapping of free carriers into more grain boundary trap sites in channel layer.

Comparative Analysis of Bandgap-Engineered Pillar Type Flash Memory with HfO&lt;sub&gt;2&lt;/sub&gt; and S&lt;sub&gt;3&lt;/sub&gt;N&lt;sub&gt;4&lt;/sub&gt; as Trapping Layer

In this paper, we fabricated a gate-all-around bandgap- engineered (BE) silicon-oxide-nitride-oxide-silicon (SONOS) and silicon-oxide-high-k-oxide-silicon (SOHOS) flash memory device with a vertical silicon pillar type structure for a potential solution to scaling down. Silicon nitride (Si3N4) and hafnium oxide (HfO2) were used as trapping layers in the SONOS and SOHOS devices, respectively. The BE-SOHOS device has better electrical characteristics such as a lower threshold voltage (VTH) of 0.16V, a higher gm.max of 0.593µA/V and on/off current ratio of 5.76×108, than the BE-SONOS device. The memory characteristics of the BE-SONOS device, such as program/erase speed (P/E speed), endurance, and data retention, were compared with those of the BE-SOHOS device. The measured data show that the BE-SONOS device has good memory characteristics, such as program speed and data retention. Compared with the BE-SONOS device, the erase speed is enhanced about five times in BE-SOHOS, while the program speed and data retention characteristic are slightly worse, which can be explained via the many interface traps between the trapping layer and the tunneling oxide.

Charge storage and data retention characteristics of forming gas-annealed Gd2O3-nanocrystal nonvolatile memory cell

Trapping characteristics of forming gas-annealed Gd2O3 nanocrystal (Gd2O3-NC) memories were studied in detail. The trapping energy can be obtained from the data retention characteristic for different absolute temperature (T). The discharging time (τ) was extracted from a linear fitting curve of the data retention characteristic. From the relationship between ln(1/τT2) and 1/kT, the trapping energy was evaluated. Based on the retention properties, the discharge mechanisms of electrons in shallow and deep traps are correlated to the charge loss time. The observed values of the trapping energy demonstrated that deep traps are passivated by hydrogen species after FGA treatment; the difference of programming and erasing (P/E) speed of the memories between the samples with- and without-FGA treatment can be explained by this passivation process. A band diagram is proposed to explain the behavior of the charge loss mechanism. The fact that the endurance of Gd2O3-NC memories are not significantly degraded by the FGA treatment indicates that, though the deep traps are passivated by hydrogen, the reliability of the Gd2O3-NC memories is not affected. The method of FGA treatment enables the determination of the discharge process in nanocrystal memories.

Improved speed and data retention characteristics in flash memory using a stacked HfO2/Ta2O5 charge-trapping layer

This paper reports the simultaneous improvements in erase speed and data retention characteristics in flash memory using a stacked HfO2/Ta2O5 charge-trapping layer. In comparison to a memory capacitor with a single HfO2 trapping layer, the erase speed of a memory capacitor with a stacked HfO2/Ta2O5 charge-trapping layer is 100 times faster and its memory window is enlarged from 2.7 to 4.8 V for the same ±16 V sweeping voltage range. With the same initial window of ΔVFB = 4 V, the device with a stacked HfO2/Ta2O5 charge-trapping layer has a 3.5 V extrapolated 10-year retention window, while the control device with a single HfO2 trapping layer has only 2.5 V for the extrapolated 10-year window. The present results demonstrate that the device with the stacked HfO2/Ta2O5 charge-trapping layer has a strong potential for future high-performance nonvolatile memory application.

Improved retention characteristic of charge-trapped flash device with sealing layer/Al 2O 3 or Al 2O 3/high- k stacked blocking layers

Although programming and erase speeds of charge trapping (CT) flash memory device are improved by using Al 2O 3 as blocking layer, its retention characteristic is still a main issue. CT flash memory device with Al 2O 3/high- k stacked blocking layer is proposed in this work to enhance data retention. Moreover, programming and erase speeds are slightly improved. In addition, sealing layer (SL), which is formed by an advanced clustered horizontal furnace between charge trapping layer and Al 2O 3 as one of the blocking layers is also studied. The retention characteristic is enhanced by SL approach due to lower gate leakage current with less defect. With the combination of SL and Al 2O 3/high- k stacked blocking layer approaches, retention property can be further improved.

Phase Change Memory and Breakthrough Technologies

Phase change memory has had issues of overwrite cycle, erase speed, and sensitivity characteristics. We found key technologies and resolved these issues. In this paper, we discuss sensitivity of phase change material, of the conventional optical disc, of femtosecond laser response, and of electrical switching of PRAM. This sensitivity comparison suggests two kinds of phase change process capability: thermal long-range structure change and localized short-range structure change.

Effect of MIM and n-Well Capacitors on Programming Characteristics of EEPROM

An electrically erasable programmable read-only memory (EEPROM) containing a stacked metal-insulator-metal (MIM) and n-well capacitor is proposed. It was fabricated using a 0.18 <TEX>$\mu$</TEX>m standard complementary metal-oxide semiconductor process. The depletion capacitance of the n-well region was effectively applied without sacrificing the cell-area and control gate coupling ratio. The device performed very similarly to the MIM capacitor cell regardless of the smaller cell area. This is attributed to the high control gate coupling ratio and capacitance. The erase speed of the proposed EEPROM was faster than that of the cell containing the MIM control gate.

Multi-layer stacked OHA and AHA tunnel barriers for charge trap flash non-volatile memory application

The tunnel barrier engineering technology is expected to provide faster programming and erasing (P/E) speeds as well as longer data retention for next generation non-volatile memory (NVM) devices. In this study, we fabricated the charge trap flash (CTF) memory devices with engineered tunneling barrier by stacking ultra thin SiO 2, HfO 2 and Al 2O 3 layers. Because the as-deposited tunneling barriers have charge trapping characteristic, the rapid thermal annealing (RTA) and forming gas annealing (FGA) processes were conducted at various temperatures to eliminate the charge trapping property in multiply stacked tunnel barriers. As a result, it is found that the optimized heat treatment condition to reduce the charge trapping and to enhance the tunneling efficiency of tunneling barriers is a combination of RTA at 800 °C and FGA at 450 °C processes. Then, metal–Al 2O 3–HfO 2–Al 2O 3–HfO 2–SiO 2–Si (MAHAHOS) structure and metal–Al 2O 3–HfO 2–Al 2O 3–HfO 2–Al 2O 3–Si (MAHAHAS) structure memory devices were fabricated and the memory characteristics were compared. The MAHAHAS structure memory device showed faster program and erase speed, stable data retention and endurance characteristics than the MAHAHOS structure memory device. Therefore, the tunnel barrier composed of Al 2O 3/HfO 2/Al 2O 3 stacked layer is applicable to embedded memory devices in System-On-Glass as a low temperature process.

Dual dielectric tunnel barrier in silicon-rich silicon nitride charge-trap nonvolatile memory

We investigated a tunnel barrier with dual (SiO2 and SiNx) dielectric layers in charge-trap nonvolatile memories to improve the program/erase speed and charge retention characteristics. Threshold voltage shift measurements performed for various stress voltages and time durations revealed that these devices had a large memory window (2–6 V) and long retention time (&amp;gt;10 years). With a decrease in the SiO2 layer thickness, the program speed increased but the erase speed decreased. The change in the program/erase speed and charge retention characteristics with the relative thickness ratio could be attributed to the asymmetric shape of the tunnel barrier. The tunneling currents were explained on the basis of Fowler–Nordheim tunneling and Frenkel–Poole emission in the asymmetric tunnel barrier.

Device characteristics of HfON charge-trap layer nonvolatile memory

The authors studied the device characteristics of thin HfON charge-trap layer nonvolatile memory in a TaN/Al2O3/HfON/SiO2/p-Si structure. A large memory window and fast erase speed, as well as good retention time, were achieved by using the NH3 nitridation technique to incorporate nitrogen into the thin HfO2 layer, which causes a high electron-trap density in the HfON layer. The higher dielectric constant of the HfON charge-trap layer induces a higher electric field in the tunneling oxide at the same voltage compared to non-nitrided films and, thus, creates a high Fowler–Nordheim tunneling current to increase the erase and programming speed. The trap level energy in the HfON layer was calculated by using an amphoteric model.

Ultrathin HfON Trapping Layer for Charge-Trap Memory Made by Atomic Layer Deposition

Charge storage characteristics of a hafnium oxynitride (HfON) charge-trapping layer prepared by atomic layer deposition in a metal-Al2O3-HfON-SiO2-Si (MAHNOS) structure are investigated. We found that an ultrathin HfON (~2.5 nm) embedded in MAHNOS has large memory window (~7.5 V at Vg = ±15 V), sufficient erase speed (Δ VFB = 4 V at -16 V/1 ms), and satisfactory data retention. From the relation of erase transient current density (J) versus tunnel oxide e-field (ETUN), we also found that the erase mechanism of MAHNOS depends on electron detrapping from HfON to Si substrates. However, MAHNOS embedding with a thicker HfON shows a poor data retention due to the increase of crystallization of the trapping layer.

Impact of Source Junctions on the Performance and Cycling-Induced Degradation of Split-Gate Flash Memory

The impacts of different source junctions on the program/erase speed and cycling degradation are studied in details for split-gate memory using source-junction-side FN erase and source-side injection program. The device with pure phosphorous source junction has faster program but slower erase speed than that with phosphorous plus arsenic source junction, mainly because of stronger coupling between floating gate and pure phosphorous junction. During program/erase cycling, the memory cell with phosphorous junction shows much higher program-VT rise but less erase-VT increase than that with phosphorous-plus-arsenic junction. For the phosphorous junction, it is found the cycling-induced damage is mainly caused by program operation near the injection point. For the phosphorous-plus-arsenic junction, however, program and erase generate almost equal amount of damage near the injection point and the source junction, respectively. Anneal after phosphorous-plus-arsenic implant improves cycling performance due to less abrupt junction.

Enhance the split-gate flash cell performance by partially decoupling the SG oxide thickness from the tunnel oxide thickness

In this paper, a method is proposed to enhance the self-aligned split-gate flash cell performance. Utilizing the different oxidation rate between silicon substrate and the heavily-doped poly-silicon sidewall of the floating gate, a rapid-thermal-oxidation step before oxide deposition is proved to be effective to decouple the tunnel oxide thickness from the select gate (SG) oxide thickness. 0.18 μm self-aligned split-gate flash cell fabricated with this method is characterized. The erase speed is shown slightly faster even with the erase voltage lowered by 1 V. The read current in erased state is improved by 70%. Good endurance and data retention performances are also demonstrated.

Electrical properties of HfO 2 charge trap flash memory with SiO 2/HfO 2/Al 2O 3 engineered tunnel layer

The program/erase (P/E) characteristic of tunnel barrier engineered charge trap flash (TBE-CTF) memory with MAHOS (Metal/Al 2O 3/HfO 2/SiO 2/Si) structure and MAHAHOS (Metal/Al 2O 3/HfO 2/Al 2O 3/HfO 2/SiO 2/Si) structure were investigated. The tunnel barrier structures for nonvolatile memory (NVM) application were designed by using the quantum–mechanical tunnel model (QM) and then the CTF memory devices were fabricated by stacking various dielectric materials for tunnel barrier, charge trap layer and blocking layer. As a result, a faster P/E speed and a longer data retention time were obtained from the MAHAHOS memory device. Especially, the program speed was enhanced by 10 4 times from 100 ms to 10 us, and the erase speed was enhanced by 10 2 times from 1 s to 10 ms. Also, the MAHAHOS device showed an improved retention characteristic compared with the MAHOS device. In addition, it is found that a high work function gate electrode (Pt) contributes to a significant reduction of data erasing time and an improved data retention characteristic of MAHAHOS memory device.

Barrier engineering in metal–aluminum oxide–nitride–oxide–silicon (MANOS) flash memory: Invited

The non-volatile memory market, especially the NAND market, has grown explosively in recent years and its business/market volume has become comparable to that of DRAM. NAND device technology has become a technology driver in physical dimension scaling because its structure and layout are simpler than DRAM and logic circuit. However, the current floating gate-type structure has inherent limiting factors in physical scaling. To overcome the scaling limit of floating gate NAND structures, a charge trap flash (CTF)-based structure is believed to show promise even though it still has issues, such as data retention and slow program erase, due to its unique gate stack structure. To improve erase speed and data retention, a barrier engineering (BE) approach for the tunneling layer and blocking layer/metal electrode shows promise for CTF devices. For the gate electrode, a stable, high WF solution is required. The large conduction band offset is necessary for the blocking oxide layer for better retention, but needs to be optimized in a sense of programming/erasing and retention. For the tunnel barrier, a high- k based tunnel barrier is a promising approach to improving erase speed and retention. However, reliability of tunnel oxide should be carefully studied. To determine the optimum gate stack for MANOS in terms of retention, P/E speed, and endurance, strategic approaches to improve device characteristics are required.

Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under nand (FN/FN) Operation

Despite significant advances in structure and material optimization, poor erase (E) speeds and high retention charge loss remain the challenging issues for charge trap flash (CTF) memories. In this paper, the dependence of SANOS memory performance and reliability on the composition of silicon nitride (SiN) layer is extensively studied. The effect of varying the Si:N ratio on program (P)/E and retention characteristics is investigated. SiN composition is shown to significantly alter the electron and hole trap properties. Varying the SiN composition from N-rich (N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> ) to Si-rich ( Si <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> ) lowers electron trap depth but increases hole trap depth, causing lower P state saturation but significant over erase, resulting in an enhanced memory window. During retention, P state charge loss depends on thermal emission followed by the tunneling out of electrons mostly through tunnel dielectric, which becomes worse for Si <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> SiN. Erase state charge loss mainly depends on hole redistribution under the influence of internal electric fields, which improves with Si <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> SiN. This paper identifies several important performances versus reliability tradeoffs to be considered during the optimization of SiN layer composition. It also explores the option for CTF optimization through the engineering of SiN stoichiometry for multilevel cell NAND flash applications.

Electroactive micro and nanowells for optofluidic storage

This paper reports an optofluidic architecture which enables reversible trapping, detection and long term storage of spectrally multiplexed semiconductor quantum dot cocktails in electrokinetically active wells ranging in size from 200nm to 5microm. Here we describe the microfluidic delivery of these cocktails, fabrication method and principal of operation for the wells, and characterize the readout capabilities, storage and erasure speeds, internal spatial signal uniformity and potential storage density of the devices. We report storage and erase speeds of less than 153ms and 30ms respectively and the ability to provide 6-bit storage in a single 200nm well through spectral and intensity multiplexing. Furthermore, we present a novel method for enabling passive long term storage of the quantum dots in the wells by transporting them through an agarose gel matrix. We envision that this technique could find eventual application in fluidic memory or display devices.

Effects of tunnel oxide process on SONOS flash memory characteristics

In this paper, various process conditions of tunnel oxides are applied in SONOS flash memory to investigate their effects on charge transport during the program/erase operations. We focus the key point of analysis on Fermi-level ( E F) variation at the interface of silicon substrate and tunnel oxide. The Si–O chemical bonding information which describes the interface oxidation states at the Si/SiO 2 is obtained by the core-level X-ray photoelectron spectroscopy (XPS). Moreover, relative E F position is determined by measuring the Si 2 p energy shift from XPS spectrums. Experimental results from memory characteristic measurement show that MTO tunnel oxide structure exhibits faster erase speed, and larger memory window during P/E cycle compared to FTO and RTO tunnel oxide structures. Finally, we examine long-term charge retention characteristic and find that the memory windows of all the capacitors remain wider than 2 V after 10 5 s.