Multi-layer stacked OHA and AHA tunnel barriers for charge trap flash non-volatile memory application

Abstract

The tunnel barrier engineering technology is expected to provide faster programming and erasing (P/E) speeds as well as longer data retention for next generation non-volatile memory (NVM) devices. In this study, we fabricated the charge trap flash (CTF) memory devices with engineered tunneling barrier by stacking ultra thin SiO 2, HfO 2 and Al 2O 3 layers. Because the as-deposited tunneling barriers have charge trapping characteristic, the rapid thermal annealing (RTA) and forming gas annealing (FGA) processes were conducted at various temperatures to eliminate the charge trapping property in multiply stacked tunnel barriers. As a result, it is found that the optimized heat treatment condition to reduce the charge trapping and to enhance the tunneling efficiency of tunneling barriers is a combination of RTA at 800 °C and FGA at 450 °C processes. Then, metal–Al 2O 3–HfO 2–Al 2O 3–HfO 2–SiO 2–Si (MAHAHOS) structure and metal–Al 2O 3–HfO 2–Al 2O 3–HfO 2–Al 2O 3–Si (MAHAHAS) structure memory devices were fabricated and the memory characteristics were compared. The MAHAHAS structure memory device showed faster program and erase speed, stable data retention and endurance characteristics than the MAHAHOS structure memory device. Therefore, the tunnel barrier composed of Al 2O 3/HfO 2/Al 2O 3 stacked layer is applicable to embedded memory devices in System-On-Glass as a low temperature process.