Abstract
In this letter, we propose a new shallow trench isolation (STI) recess effect on the self-aligned STI of nand Flash memory devices. In the current nand Flash cell design, increasing the recess depth of STI recess yields a higher gate coupling ratio and lower floating-gate (FG) interference to achieve better immunity to process fluctuation. However, the current design is limited by significantly slower Fowler–Nordheim (FN) erase speed and degraded channel characteristics. Slow erase speed is caused by the accumulation of holes around channel edges, while the degraded channel is owing to FN cycling stress-induced interface damage. The proposed STI recess structure maintains a proper distance between the channel edge and the control gate, as well as blocks the FG interference without increasing cell-to-cell spacing.
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