Barrier engineering in metal–aluminum oxide–nitride–oxide–silicon (MANOS) flash memory: Invited

Abstract

The non-volatile memory market, especially the NAND market, has grown explosively in recent years and its business/market volume has become comparable to that of DRAM. NAND device technology has become a technology driver in physical dimension scaling because its structure and layout are simpler than DRAM and logic circuit. However, the current floating gate-type structure has inherent limiting factors in physical scaling. To overcome the scaling limit of floating gate NAND structures, a charge trap flash (CTF)-based structure is believed to show promise even though it still has issues, such as data retention and slow program erase, due to its unique gate stack structure. To improve erase speed and data retention, a barrier engineering (BE) approach for the tunneling layer and blocking layer/metal electrode shows promise for CTF devices. For the gate electrode, a stable, high WF solution is required. The large conduction band offset is necessary for the blocking oxide layer for better retention, but needs to be optimized in a sense of programming/erasing and retention. For the tunnel barrier, a high- k based tunnel barrier is a promising approach to improving erase speed and retention. However, reliability of tunnel oxide should be carefully studied. To determine the optimum gate stack for MANOS in terms of retention, P/E speed, and endurance, strategic approaches to improve device characteristics are required.