Erase Speed Research Articles

Memory effects based on random networks of single-walled carbon nanotubes

We have fabricated memory devices based on random networks of single-walledcarbon nanotubes (SWNTs) on a glass substrate. The characteristics ofthe nonvolatile memory were investigated as a function of gate voltage,pulse time, and temperature. The program/erase window was greater thanapproximately 3.2 V. The gate voltage sensitivity of the erase speed was greater (∼1.9 times) than that of the program speed. The activation energy was about 0.273 eV. Themechanism could be explained from the polarization of water molecules, and may providean important insight into the program/erase operation of memory devices. We have alsodiscussed a fast erase speed due to a work function difference and oxide trapped charges.

TCAD-based demonstration of improved spacer select gate EEPROM cell architecture

An SSG EEPROM (Spacer Select Gate Electrically Erasable Programmable Read Only Memory) cell is proposed for improvement in program and erase operations and compared with a conventional one. Electrical characteristics of the conventional SSG EEPROM cell in program and erase operations are simulated, analyzed, using TCAD software tools, and verified against measurements. The improved SSG EEPROM cell reaches a target threshold voltage 3.9 V at 0.26 ms after the program operation starts, whereas the conventional cell at 1.7 ms. The Fowler–Nordheim tunneling current and floating gate charge of the improved EEPROM cell during the program operation are 5 times and 46% larger than those of the conventional cell, respectively. Scaling down the SSG EEPROM cells improves both the program and erase speeds. As the floating gate length of the conventional SSG EEPROM cell is reduced from 0.21 to 0.1 μm, the 0.1-μm EEPROM cell reaches the target program threshold voltage 25 times faster than the 0.21-μm cell.

Physical Model of Field Enhancement and Edge Effects of FinFET Charge-Trapping NAND Flash Devices

The physical model for field enhancement (FE) and the edge effects of body-tied FinFET charge-trapping NAND Flash devices are extensively studied in this paper. First, analytical equations are derived to provide insight to the FE effect for FinFET devices, and these analytical results are validated by 3-D TCAD simulation and experimental verification. Next, complicated programming and erasing characteristics and transconductance and subthreshold slope (gm/SS) behaviors are completely explained by the nonuniform injection behavior along various corner edges in FinFET. FE allows high program and erase speed and larger memory window. On the other hand, the edge effect complicates the device DC I-V, as well as programming and erasing characteristics, and these must be taken into account in memory circuit design.

Pulse-$IV$ Characterization of Charge-Transient Behavior of SONOS-Type Devices With or Without a Thin Tunnel Oxide

The transient behavior of SONOS-type devices was investigated for the first time using pulse- IV technique. Three kinds of SONOS devices are studied: SONS (without top oxide), SONoS (with a thin top oxide), and SoNOS (with a thin bottom oxide). Devices with or without a thin tunnel oxide were able to provide very fast charge injection/detrapping, but their charge-transient behavior cannot be accurately monitored by conventional DC-IV method. By using specific pulse-IV setup for memory, we can measure the drain current response immediately after programming and erasing, as well as the fast charge relaxation under various reliability tests. The program and erase transient behavior shows that all devices are easily programmed and erased within 1 mus at low gate voltages (<6 V). Moreover, SONS shows the fastest program and erase speeds because of the absence of tunnel oxide, and silicon nitride has very low barrier height that offers fast injection. We have also examined the charge relaxation under various field and temperature conditions and found that the charge loss mainly came from external charge injection during retention, not from detrapping through thermionic emission.

Investigations on the Impact of the Parasitic Bottom Transistor in Gate-All-Around Silicon Nanowire SONOS Memory Cells Fabricated on Bulk Si Substrate

Gate-all-around (GAA) Si nanowire SONOS memory cells (SNWMs) have been fabricated on Si substrate using fully epi-free compatible CMOS technology. A parasitic bottom SONOS memory (PBM) was formed when the SNWM was fabricated on bulk Si substrate. The impact of the PBM on the performance of the SNWM is investigated in this paper. The PBM shows a slower program speed, a faster erase speed, and worse retention characteristics than the SNWM. Therefore, the PBM severely degrades the performance of the SNWM due to its slower program speed and worse retention characteristics, and should be carefully controlled for the SNWM based on bulk Si substrate.

Erase and Retention Improvements in Charge Trap Flash Through Engineered Charge Storage Layer

The simultaneous improvement in the erase and retention characteristics in a TANOS (TaN-Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> -SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -Si) flash memory transistor by utilizing the band-engineered and compositionally graded SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> trap layer is demonstrated. With the process optimizations, a > 4V memory window and excellent 150 degC 24-h retention (0.1-0.5 V charge loss) for a programmed DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> = 4V with respect to the initial state are obtained. The band-engineered SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> charge storage layer enables flash scaling beyond the floating-gate technology with a promise for improved erase speed, retention, lower supply voltages, and multilevel cell applications.

NAND 전하트랩 플래시메모리를 위한 p채널 SONOS 트랜지스터의 특성

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

Reliability and Processing Effects of Bandgap-Engineered SONOS (BE-SONOS) Flash Memory and Study of the Gate-Stack Scaling Capability

In this paper, the reliability properties of bandgap-engineered SONOS (BE-SONOS) devices with various processing methods are extensively studied. BE-SONOS employs a multilayer O1/N1/O2/N2/O3 stack, where O1/N1/O2 serves as a bandgap-engineered tunneling barrier that provides an efficient hole-tunneling erase but eliminates the direct-tunneling leakage. BE-SONOS can overcome the fundamental limitation of the conventional SONOS, for which fast erase speed and good data retention cannot be simultaneously achieved. In this paper, a comprehensive understanding of BE-SONOS reliability is reported, including the processing effects of the critical ONO barrier (O1/N1/O2), the trapping layer (N2), and the top blocking oxide (O3). Moreover, the capability of dielectric scaling is also evaluated. Lower P/E voltages, good P/E cycling endurance, and data retention are maintained when N2 and O3 are further scaled to 60 . The results in this paper provide design and processing guidelines for optimizing the performance and reliability of BE-SONOS flash memory devices.

Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell

This letter presents a high-speed silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory cell in gate-all-around Si-nanowire (NW) architecture, which is fabricated by using a top-down process technology. The NW cell exhibits faster program and erase (P/E) speed compared to the corresponding planar device; 1 mus for programming and 1 ms for erasing at VGS = plusmn11 V with a threshold voltage shift DeltaVTH of 2.6 V using the Fowler-Nordheim tunneling mechanism. At these P/E conditions, the planar device does not show appreciable change. The improvement is originated from: 1) increased electric field at the Si-SiO2 interface; 2) reduced effective tunnel barrier width; and 3) low electric field in the blocking oxide, as analyzed through simulation. In addition, good data retention makes the NW-based SONOS cell a potential candidate for future high-speed low-voltage NAND-type nonvolatile Flash memory applications.

New erase head for kanban card size thermal rewritable media

The benefits of thermal rewritable technology can be seen in working for traditional conservation situations &#x2013; the idea of saving trees, reducing CO2 gas emission and cutting down waste material and reducing the print material cost over time. They can also be found on more application specific situations such as a data security conscious world &#x2013; since the print media is reused, there is no need for the internal information leaking out and documentation shredding is not required.Advantages of thermal rewritable printing over conventional printing can be fully exploited in a closed system environment like commercial or industrial applications where the rewritable media can be recovered at the end of processes. Physical distribution within manufacturing cycle such as parts supply of assembly plant, for example, will be an ideal situation to take advantage of this technology in order to increase productivity and efficiency.Highly publicized and successful application is an adaptation of rewritable technology in &#x201C;just-in-time&#x201D; kanban system. In order to meet the demand of better erasing device, the new erase head which is one of the key components for the technology was developed. The HDA-2310 has erase width of 210 mm which will accommodate the kanban card size and erase speed of 100 mm/sec which is on par with the high speed thermal printhead used for rewritable application.

Study of Fluorine Incorporation in the Blocking Oxide of MANOS-Type Flash Memory Devices

The effect of high-pressure fluorine annealing (HPFA) at 400°C for 20 min on metal-alumina-nitride-oxide-silicon (MANOS)-type flash memory devices is investigated in this study. After HPFA, X-ray photoelectron spectroscopy data show that the fluorine concentration is nearly 10% at the alumina top surface and decreases with depth. The HPFA replaces Al-O bonds with Al-F bonds in the Al 2 O 3 . This F incorporation results in a reduced leakage current at high electric field (> -16 MV/cm) and improves blocking efficiency. MANOS device characteristics of erase speed, endurance, and retention are all improved. © 2008 The Electrochemical Society. [DOI: 10.1149/1.2978962] All rights reserved.

Design of Unique Four-Bit/Cell Polycrystalline Silicon–Oxide–Silicon Nitride–Oxide–Silicon Devices Utilizing Vertical Channel of Silicon Pillar

Unique four-bit/cell polycrystalline silicon–oxide–silicon nitride–oxide–silicon (SONOS) devices with separated ONOs utilizing the vertical channel of a silicon pillar, denoted as silicon pillar vertical-channel SONOS (SPVC-SONOS) devices, were designed to increase memory density. A narrow charge distribution and improved data retention were achieved owing to the separation of the storage nitride layers. An analytical model of the transient characteristics for investigating the effects of the dielectric composition and the erase speed, which was dependent on the erase voltage, was developed. Floating nodes acting as a trap site were added in the nitride layer to simulate the program characteristics using the conventional device simulator medici. The channel hot-electron-injection program, Fowler–Nordheim tunneling erase, and reverse mode read characteristics were estimated to verify the operation of the novel four-bit/cell SPVC-SONOS devices. The proposed unique four-bit/cell SPVC-SONOS devices can be used to increase memory density.

A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for nand-Type Flash Memory

A body-tied FinFET bandgap engineered (BE)-silicon-oxide-nitride-oxide-silicon (SONOS) nand Flash device is successfully demonstrated for the first time. BE-SONOS device with a BE oxide-nitride-oxide barrier is integrated in the FinFET structure with a 30-nm fin width. FinFET BE-SONOS can overcome the unsolvable tradeoff between retention and erase speed of the conventional SONOS. Compared with the current floating-gate Flash devices, FinFET BE-SONOS provides both retention and erase-speed performance, while eliminating the scaling limitations and is, thus, an important candidate for further scaling of nand Flash

Memory characteristics of Au nanocrystals embedded in metal–oxide–semiconductor structure by using atomic-layer-deposited Al2O3 as control oxide

The nonvolatile memory characteristics of metal–oxide–semiconductor (MOS) structures containing Au nanocrystals in the Al2O3/SiO2 matrix were studied. In this work, we have demonstrated that the use of Al2O3 as control oxide prepared by atomic-layer-deposition enhances the erase speed of the MOS capacitors. A giant capacitance–voltage hysteresis loop and a very short erase time which is lower than 1 ms can be obtained. Compared with the conventional floating-gate electrically erasable programmable read-only memories, the erase speed was promoted drastically. In addition, very low leakage current and large turn-around voltage resulting from electrons or holes stored in the Au nanocrystals were found in the current–voltage relation of the MOS capacitors.

A New Operating Scheme by Switching the Polarity of Program/Erase Bias for Partially Oxidized Amorphous-Si-Based Charge-Trap Memory

In this brief, the authors propose a new program/erase (P/E) scheme for NAND-type partially oxidized amorphous-Si (a-Si)-based charge-trap memory in which the P/E voltages are interchanged into negative/positive ones, respectively. In the a-Si memory, the erasing speed was found to be faster than the programming speed, and therefore, the new scheme has been chosen to keep the program speed faster than the erase speed for the NAND operation. The P/E speeds in the new scheme increase at least ten times as those in the conventional P/E scheme. It is also shown that four-level memory states can be achieved via Fowler-Nordheim tunneling by applying programming voltage of -16, -18, and -20 V for each level during only 40 mus together with erasing voltage pulse (+20 V, 1 ms). These results indicate that the new P/E scheme is more effective than the conventional scheme for operating the partially oxidized a-Si-based memories

단일층 다결정 실리콘 Flash EEPROM 소자의 제작과 특성 분석

In this paper, we propose the single poly-Si Flash EEPROM device with a new structure which does not need the high voltage switching circuits. The device was designed, fabricated and characterized. From the measurement results, it was found that the program, the erase and the read operations worked properly. The threshold voltage was 3.1 V after the program in which the control gate and the drain were biased with 12 V and 7 V for , respectively. And it was 0.4 V after the erase in which the control gate was grounded and the drain were biased with 11 V for . On the other hand, it was found that the program and the erase speeds were significantly dependent on the capacitive coupling ratio between the control gate and the floating gate. The larger the capacitive coupling ratio, the higher the speeds, but the target the area per cell. The optimum structure of the cell should be chosen with the consideration of the trade-offs.

Data Retention Characteristics of Nitride-Based Charge Trap Memory Devices with High-k Dielectrics and High-Work-Function Metal Gates for Multi-Gigabit Flash Memory

The data retention characteristics of nitride-based charge trap memories using metal–oxide–nitride–oxide–silicon (MONOS) structures employing high-k dielectrics and high-work-function metal gates have been investigated. The fabricated MONOS devices with structures of TaN/Al2O3/Si3N4/SiO2/ p-Si show fast program/erase characteristics with a large memory window of greater than 6 V at program and erase voltages of ±18 V. From a bake retention test at high temperatures (200, 225, 250, and 275 °C), it is expected to take more than 40 years to lose less than 0.5 V charge loss at 85 °C. In this paper, we present an optimized cell structure for both improved data retention and erase speed, as well as a systematic study on the charge decay process in MONOS-type flash memory for high-density device applications.

A novel self-aligned highly reliable sidewall split-gate flash memory

A self-aligned sidewall split-gate Flash memory cell is fabricated with overerase immunity. Particularly, the sidewall corner of the floating-gate is deliberately rounded to release the electric field lines encountered in the poly-to-poly erase. The unit cell size of 12.7 F/sup 2/ (F is the feature size), formed in a 32-Mb NOR architecture, and the acceptable erase speed of 20 ms for block erase (512 K bits, 16 pages) are quite competitive. Endurance cycles up to 10/sup 5/ confirm the novel cell to be highly reliable as compared with the conventional source-side erase scheme. The bake experiment at 250/spl deg/C before and after program/erase cycles indicates the cell not only free of extrinsic defects in the manufacturing process but also experiencing excellent retention characteristics. Disturb effects during the programming and read-out operations are examined in detail and the operating conditions for disturbs inhibition are readily determined. We eventually elaborate on the differences between the proposed cell structure and existing ones, as well as on the NAND architecture application.

A novel high-/spl kappa/ SONOS memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si structure for fast speed and long retention operation

A novel high-/spl kappa/ silicon-oxide-nitride-oxide-silicon (SONOS)-type memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si (MATHS) structure is reported for the first time. Such MATHS devices can keep the advantages of our previously reported TaN/HfO/sub 2//Ta/sub 2/O/sub 5//HfO/sub 2//Si device structure to obtain a better tradeoff between long retention and fast programming as compared to traditional SONOS devices. While at the same time by replacing hafnium oxide (HfO/sub 2/) with aluminum oxide (Al/sub 2/O/sub 3/) for the top blocking layer, better blocking efficiency can be achieved due to Al/sub 2/O/sub 3/'s much larger barrier height, resulting in greatly improved memory window and faster programming. The fabricated devices exhibit a fast program and erase speed, excellent ten-year retention and superior endurance up to 10/sup 5/ stress cycles at a tunnel oxide of only 9.5 /spl Aring/ equivalent oxide thickness.

Charge-trapping memory cell of SiO2∕SiN∕high-k dielectric Al2O3 with TaN metal gate for suppressing backward-tunneling effect

We present a device structure of SiO2∕SiN∕Al2O3 (SANOS) with tantalum nitride (TaN) metal gate. When TaN metal gate is applied for the SANOS structure instead of commonly used n-type poly-silicon, the unwanted backward Fowler–Nordheim tunneling current of electron through the top oxide is significantly suppressed owing to its higher work function and better compatibility with high-k dielectrics. As a result, the program∕erase speed is significantly improved and the erase threshold voltage (VTH) can be obtained to be negative voltage of −3.5V.