Encoder Circuit Research Articles

Design and Simulation of Balanced Ternary Priority Encoder

The priority encoder is a frequently used circuit in binary logic and is mostly used for interrupt handling and other priority resolving tasks. On the other hand, Ternary computing has tremendous potential for handling a wide variety of functions involving large range of numbers, whereas, the literature is confined to very basic functions. The proposed balanced priority encoder circuit that uses three logic symbols i.e.−1,0 and 1. In this study, we develop the design and architecture of a Ternary Priority Encoder circuit with an estimation of its time complexity. The intricacy of the circuit under consideration is supposed to highlight the capabilities of the ternary logic system. The flexibility of the circuit lies in its implementation using simple binary counterparts. As there is no simulator available for Ternary Logic, we have developed a Balanced Ternary Logic Simulator which is freely available from https://github.com/Aggtur11/Ternary-Logic-Simulator. The logic behaviour of the proposed priority encoder circuits is verified using the developed simulator.

Design of unbalanced 9:2 ternary encoder and 2:9 ternary decoder circuits in resistive random access memory and carbon nanotube field effect transistor technology

SummaryMultivalued logic (MVL) offers higher information density as compared with binary logic systems for an equal number of digits. In a ternary microprocessor, memory access is the most time‐ and power‐consuming action. In order to design a ternary computer, the possibilities for designing ternary encoders and decoders must be examined. This paper presents the designs of 9:2 unbalanced ternary encoder (TENC) and 2:9 unbalanced ternary line address decoder (TDEC) based on novel designs of standard ternary inverter (STI), ternary NAND (TNAND), and ternary NOR (TNOR) logic gates using resistive random‐access memory (RRAM) and carbon nanotube field effect transistor (CNTFET) technology. The simulation results indicate an improvement in performance parameters such as power consumption, delay, power–delay product (PDP), and component count of the proposed circuits in comparison with the different existing counterparts. Moreover, a detailed analysis is carried out on the impact of different process, voltage, and temperature (PVT) variations on the performance metrics, including propagation delay, power consumption, and PDP of the 9:2 unbalanced ternary encoder and 2:9 unbalanced ternary line address decoder. The proposed ternary encoder circuit shows an improvement of 62% in delay, 71% in power consumption, 88.6% improvement in PDP, and 53% reduction in CNTFET count, whereas the ternary decoder circuit exhibits an improvement of 6.6% and 94% in delay and 43% and 94% improvement in power consumption, respectively. Moreover, the CNTFET count is reduced by 16.07% and 46%.

Design of Reversible Quantum Vigenere Cryptographic Cipher in QCA and IBMQ Platforms for Secure Nanocommunication

Using cryptography correctly is crucial in the current situation to safeguard data and ensure data security during data transfer. In this digital era, messages must be appropriately encrypted and decoded to prevent data misuse and ensure its accessibility to the intended recipient. Conventional cryptography techniques mostly depend on the mathematical intricacy of the encoding functions and the shared key. One such encoding approach that we may take into consideration is the Vigenere cipher algorithm. In this study, we want to apply this strategy utilizing reversible logic with the assistance of two helpful tools, namely, IBM Quantum (IBMQ) and QCADesigner. The encoder and decoder circuits for the Vigenere cipher are therefore proposed in this work in QCADesigner by utilizing Peres and DG gates in quantum-dot cellular automata (QCA) that consist of a single layer with 42 cells for encryption and 47 cells for decryption. The proposed circuit outperforms the existing ones concerning area, cell count and latency. Given that the layouts’ energy consumption is assessed, it is guaranteed that the QCA nanodevice might serve as a stand-in platform for the creation of reversible circuits. The same simulation outcome was also obtained while building the identical circuits in a quantum presentation using IBMQ. The two applications are closely connected and both rely on quantum concepts. The outcomes are therefore verified for each of the two situations. The reversible Vigenere cipher technique enhances data security. Further sophisticated low-power nanoscale lossless nanocommunication architecture may be created with the help of the suggested circuits.

High Logic Density Cyclic Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit for JESD204C Controller

High Logic Density Cyclic Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit for JESD204C Controller

Efficient Nano-Scale Design of TIEO Based Reversible Logic Toffoli Gate Priority Encoder in Quantum-Dot Cellular Automata

The goal of this research is to create a QCA-based reversible priority encoder. It is one of the most crucial parts of the encoding and decoding process. This novel nanotechnology, known as quantum-dot cellular automata (QCA), shows promise as a foundation for the development of reversible circuits. This paper proposes a simple, reversible, 4-2 line priority encoder design for the QCA platform. Using the simple and cheap Toffoli gate architecture, a reversible encoder circuit may be built. To analyze the proposed designs’ structural soundness, the simulation program QCA Designer is used.

Secure nano-communication framework using RSCV cryptographic circuit in IBM Q

In the cryptographic domain, quantum and its real-time hardware simulation make it easier to secure data during communication. Here, using quantum logic, a unique encryption technique called Reversible select, cross, and variation (RSCV) encryption and decryption, which involves swapping input data halves, is shown. In this article using IBM Q, we created a cryptographic encoder and decoder circuit design utilizing various quantum gates. Based on the encoder/decoder circuit, a simple nanocommunication framework is proposed. Further, to explore the application of the noise model, how to utilize this model to create noisy replicas of these quantum circuits to research the impacts of noise that occur for actual device output is shown. To reduce measurement mistakes, measurement calibration is performed using qiskit ignis model. Preparing all 2n basis input states and calculating the likelihood of counting in the other basis states are the key concepts. The percentage improvement we achieved is 40%, 30%, and 30%, respectively, compared to earlier ones, in RSCV encryption, decryption, and RSCV cryptographic communication architecture for fake provider noise error model. It is feasible to adjust the average outcomes of an additional interesting experiment using these calibrations.

Ternary encoder and decoder designs in RRAM and CNTFET technologies

A possible way for the very large scale integration (VLSI) industry to keep up with the pace of high density, computational capability, and energy efficiency is to look into some technologies ahead of binary logic. In recent years, multiple-valued logic (MVL) has caught the notable attention of digital system designers. The carbon nanotube field effect transistor (CNTFET) has been exclusively used for the implementation of MVL circuits. Resistive random-access memory (RRAM) offers a very durable option for executing the MVL due to its capability of storing various resistance states in one cell. In this paper, a ternary 9:2 encoder and a ternary 2:9 decoder have been designed and simulated using the proposed RRAM-based ternary logic gates with standard 32nm CNTFETs. In comparison to other ternary circuits in the literature, the proposed CNTFET RRAM-based ternary logic circuits show less power consumption, delay, and power delay product (PDP). The power of the CNTFET RRAM-based proposed ternary inverter (TI), ternary NAND (TNAND), and ternary NOR (TNOR) is 32.78%, 51.48%, and 24.14% less than the lowest power of the other designs under consideration. The PVT variations and reliability of the proposed encoder and decoder circuits have also been studied.

Design of CRC circuit for 5G system using VHDL

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.

Design of CRC circuit for 5G system using VHDL

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.

Design of Modified Booth’s Encoder Using SPST technique

This paper presents the design and implementation of signed-unsigned Modified Booth Encoding (SUMBE) multiplier. The present Modified Booth Encoding (MBE) multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. Therefore, this paper presents the design and implementation of SUMBE multiplier. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign bit of the operands and generating an additional partial product the SUMBE multiplier is obtained. The Carry Save Adder (CSA) tree and the final Carry Look ahead (CLA) adder used to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. The proposed radix-2 modified Booth algorithm MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC.

Design of Wallace Tree Encoder for Flash ADC

Analog to digital converter plays a very important role in today’s digitized world as they have wide range of applications. Wallace tree encoder is an effective hardware implementation in VLSI circuits that is utilized for the analogue to digital conversion process. The Wallace tree encoder transforms thermometer code into binary code in an ADC. The suggested flash digital to analogue converter confirmed the energy, and speed. The proposed technique provides Less Delay, Less Power Consumption, and a lesser number of transistors compared to existing techniques. In this project, the proposed transmission gate full adder technique provide Less Delay, Less Power Consumption, Better Power Delay Product and a lesser number of transistors. The proposed encoder is made to count the 1s available to the logic gates for designing ROM encoders and fat tree conversion. The power may be conserved by building a low power, high performance Wallace tree encoder implementing transmission gate logic and modified full adders since Wallace tree encoder uses more power. The proposed system focuses at lowering the transistor count to improve power efficiency and delay comparator, and it is effective in minimizing the bubble errors. The Wallace tree encoder is designed by using transmission gate based full adder circuits. The proposed designs are designed and simulated using LTspice Tool with 45nm CMOS technology. The power consumption of the encoder circuit must be decreased in order to create a low power Flash ADC. The power consumption of this encoder changes noticeably when the internal full adder circuit is modified

Comments on “New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application”

This paper comments on the some mistakes which have been observed in Tripathi et al. (2023) [1]. We have specifically pointed out the following mistakes of Tripathi et al. (2023) [1].i) Presented (41, 32) SEC-DAEC-TAEC H-matrix in Fig. 3 of Tripathi et al. (2023) [1].ii) Presented error detection and correction coverage in Table 6 of Tripathi et al. (2023) [1].The corrected versions of the above mentioned mistakes have been presented in this paper. Also the FPGA-based synthesis result of corrected encoder and decoder circuits based on the corrected (41, 32) H-matrix have been presented here.

Implementation of Novel Block and Convolutional Encoding Circuit Using FS-GDI

A novel implementation of Block and Convolutional encoding circuits approach using Gate Input Diffusion-Full Swing (FS-GDI) and Complementary Metal Oxide Semiconductor (CMOS) logic styles has been presented. Performance analysis of the proposed encoding circuits has been performed using Cadence Virtuoso (CV) S/W package. The performance metrics of FS-GDI-based encoding circuits have been compared with traditional CMOS-based designs. The proposed encoding circuits involve Block Hamming (15, 11), Convolutional (2, 1, 3), and Recursive Systematic Convolutional (2, 1, 2) encoding circuits; these presented circuits are simulated and tested using a word length of 11 bits. The simulation experiments revealed that the proposed implemented circuits achieve delay time improving by 27.91% and 33.27% for Hamming (15, 11) and Convolutional (2, 1, 3) codes, respectively. The simple proposed RSC encoder performs better than the Convolutional (2, 1, 3) due to shorter constraint length and less H/W complexity. On the other hand, the Transistor Count-Hardware (TC-H/W) is enhanced by 50% for the Block and Convolutional encoding based on employing area-efficient FS-GDI-XOR gate. From the analysis of the results, the proposed designs achieve efficient power and delay optimization of Hamming and Convolutional encoding utilizing the FS-GDI logic style. Also, it is clear that the characteristics of the proposed encoding circuits are vital and effective in the digital signal processing circuits and encoding/decoding schemes implementation in low-power wireless networks.

An 8B/10B parallel encoder design for the polarity pre-processing

To tackle the high latency and slow encoding speed of 8B/10B encoder circuits in high-speed serial interfaces, a parallel structure for polarity pre-processing based on logic operations is proposed to optimize encoder performance in this article. Firstly, the encoding process is divided into polarity pre-processing and coding two pipeline stages. This method equals each stage’s delay and decreases the coding waiting period. Additionally, the structure employs polarity pre-processing to optimize the critical delay paths into multi-stage heterodyne gates in series. Therefore, the effect of the number of input bytes on the critical delay path can be significantly reduced. The effectiveness of our proposed encoder is demonstrated to encode 4-byte loads by VCS simulation and synthesized using Synopsys’ Design Compiler tool upon the SMIC 65nm process. Results show that a high operating frequency of 909MHz with a 2245.68µm2 footprint area can be achieved. Compared with the cascaded and polarity-selective structures, the proposed framework has advantages in terms of speed and resource usage. These advantages greatly help to meet the high-speed transmission requirement.

Time-Comparator Neural Circuits of Gymnotiform Electric Fishes.

Weakly electric fish possess electrosensory neural systems that are dedicated to detect microsecond time differences between sensory signals. Many features of this timing system, such as electroreceptor encoding, time-locked responses, and time-comparator neural circuit, are shared by closely related as well as distantly related electric fishes. The appearance and location of the time-comparator neural structures, however, are different among species. The timing systems of different electric fish species are compared.

Design of Sixteen-Input Priority Encoder with DNA Nano Switches

With the application of DNA computing in more and more fields, the tasks are becoming more and more complex, and the scale of DNA circuits is gradually increasing. However, the current investigation of largescale circuits of DNA molecules is still a challenge. So it is crucial to optimize the performance of large-scale DNA circuits. In this paper, a large-scale digital logic circuit 16-Input-5-Output Priority Encoder is realized by using the DNA nano switches for the first time. The simulation of the 16-Input-5-Output Priority Encoder circuit shows that this method solves the problems of NOT gate instability and optimizes the DNA circuit in terms of reaction time, circuit complexity, and experimental difficulty. This paper proves the feasibility and superiority of using DNA nano switches to realize large-scale circuits, provides a new idea for realizing large-scale DNA circuits, and brings new development for the application of DNA circuits in biosensor, DNA complex computing and other fields.

Implementation of Fault-Tolerant Encoding Circuit Based on Stabilizer Implementation and "Flag" Bits in Steane Code.

Quantum error correction (QEC) is an effective way to overcome quantum noise and de-coherence, meanwhile the fault tolerance of the encoding circuit, syndrome measurement circuit, and logical gate realization circuit must be ensured so as to achieve reliable quantum computing. Steane code is one of the most famous codes, proposed in 1996, however, the classical encoding circuit based on stabilizer implementation is not fault-tolerant. In this paper, we propose a method to design a fault-tolerant encoding circuit for Calderbank-Shor-Steane (CSS) code based on stabilizer implementation and “flag” bits. We use the Steane code as an example to depict in detail the fault-tolerant encoding circuit design process including the logical operation implementation, the stabilizer implementation, and the “flag” qubits design. The simulation results show that assuming only one quantum gate will be wrong with a certain probability p, the classical encoding circuit will have logic errors proportional to p; our proposed circuit is fault-tolerant as with the help of the “flag” bits, all types of errors in the encoding process can be accurately and uniquely determined, the errors can be fixed. If all the gates will be wrong with a certain probability p, which is the actual situation, the proposed encoding circuit will also be wrong with a certain probability, but its error rate has been reduced greatly from p to compared with the original circuit. This encoding circuit design process can be extended to other CSS codes to improve the correctness of the encoding circuit.

Numerical analysis of all-optical silicon microring resonator-based cyclic redundancy check encoder

Data are transmitted at a higher rate over long and short distances to fulfill the global requirement using all-optical (AO) technology. The reliability or accuracy of data transmission is also a key factor along with the higher data rate to achieve today’s desire perfectly. The cyclic redundancy check (CRC) code is a powerful, robust, and widely used error detecting code for data communication system and storage devices to find any unintentional changes during transmission. A (7, 4) CRC encoder has been analyzed numerically using AO silicon microring resonator (MRR) at a high-operational speed of 260 Gbps. CRC encoder is designed using MRR-based XOR gates and D flip flops. The proposed CRC encoder circuit is validated through MATLAB simulation. The optimization of essential parameters is accomplished through simulation against various metrics. These parameters could be utilized for practical execution of this design.

A Novel Architecture Implementation Using Multi Scale Shared Residual Network from Remote Sensing Images for Extracting Water Bodies

Accurate data acquisition plays a vital role in crucial time period. Now a days so many real situations are suffering with accurate data prediction during disaster period. Flood zone identification is interlinked with extraction of water bodies to estimate disaster situation. So many limitations observed in the traditional waterbody detection methods but it is very important for the real situations. This paper proposes all the limitations of previous methods can be overcome with support of semantic segmentation of deep convolution network of multi scale shared residual network (MSSResNet) with CBAM blocks using satellite imagery. Because of residual blocks inserting in to encoder circuit reducing network degradation problems. Introducing depth wise convolutions to increase the performance of feature extraction property by using CBAM blocks with expanded receptive fields.

VHDL implementation of 16x16 multiplier using pipelined 16x8 modified Radix-4 booth multiplier

ABSTRACT Rapidly growing technology has increased the demand for digital signal processing applications that are fast and effective in real-time. One of the basic operations frequently required in these applications is the multiplication operation. There is a need to develop a multiplier with high speed, less area, and low power consumption to improve its performance. One of the fastest multiplier circuits is the Radix-4 Booth multiplier. Booth encoder reduces the number of partial products and hence the number of additions. The pipeline scheme is one of the most used designs to accelerate the multiplier performance. In this paper, two designs are presented. The first proposed design aims to reduce the delay of the multiplication operation of a 16 × 16 multiplier. This design uses a pipeline scheme differently by partitioning the input into two parts and overlapping their processing. The second proposed design reduces the multiplier area by applying enhancements in the modified booth encoder circuit. The proposed circuits are synthesized using XILINX ISE 14.7 and realized using ML605 Virtex 6 FPGA board. The first proposed design achieves higher speed, lower power consumption, and less area than the prior design. The second proposed design achieves more area and power consumption reduction.