An 8B/10B parallel encoder design for the polarity pre-processing

Abstract

To tackle the high latency and slow encoding speed of 8B/10B encoder circuits in high-speed serial interfaces, a parallel structure for polarity pre-processing based on logic operations is proposed to optimize encoder performance in this article. Firstly, the encoding process is divided into polarity pre-processing and coding two pipeline stages. This method equals each stage’s delay and decreases the coding waiting period. Additionally, the structure employs polarity pre-processing to optimize the critical delay paths into multi-stage heterodyne gates in series. Therefore, the effect of the number of input bytes on the critical delay path can be significantly reduced. The effectiveness of our proposed encoder is demonstrated to encode 4-byte loads by VCS simulation and synthesized using Synopsys’ Design Compiler tool upon the SMIC 65nm process. Results show that a high operating frequency of 909MHz with a 2245.68µm2 footprint area can be achieved. Compared with the cascaded and polarity-selective structures, the proposed framework has advantages in terms of speed and resource usage. These advantages greatly help to meet the high-speed transmission requirement.