Design of High performance MIPS-32 Pipeline Processor

Abstract

The paper describes the design and synthesis of a basic 5 stage pipelined MIPS-32 processor for finding the longer path delay using different process technologies. The large propagation delay or critical path within the circuit and improving the hardware which causes delay is a standard method for increasing the performance. The organization of pipeline stages in such a way that pipeline can be clocked at a high frequency. The design has been synthesized at different process technologies targeting using Spartan3, Spartan6, Virtex4, Virtex5 and Virtex6 devices. The synthesis report indicates that critical path delay is located in execution unit. The maximum critical path delay is 41.405ns at 90nm technology and minimum critical path delay is 6.57ns at 40nm technology. The performance comparison result at different technologies shows that pipeline processor can work at 178MHz in 40nm technology i.e. 49.7% better than other technologies. KeywordsMIPS Processor, Datapath, ALU, register file, pipeline