Exact path sensitization in timing analysis

Abstract

of a direct implementation of this criterion. This paper presents the first critical path finding tool based on the exact criterion. It offers therefore better results in comparison with all other approaches, since these are based on approximations of this criterion. Timing verification is an important aspect in chip design. However, the growing complexity of combinational circuits increases the total number of false paths, which demands fast and accurate false path elimination methods. Several approaches have been presented in literature, but all are based on approximations of the exact criterion, and offer no exact results. This paper presents the first implementation of the exact criterion. Experiments show that this tool is much more accurate in comparison with other approaches. The rest of this paper is organized as follows. Section 2 discusses the exact and other criteria. A description of the proposed algorithm is given in section 3. Then the two steps responsible for eliminating false paths will be described in section 4. Section 5 discusses the results obtained by the proposed tool. Finally we will finish this paper with the conclusions of section 6. 1. Introduction maximum operational frequency of a circuit is determined by the maximum propagation delay of its combinational parts, which is defined as the longest delay it takes for a signal to propagate from a primary input to a primary output. In other words, the maximum delay of a combinational part is equal to the length of its critical paths. A straightforward approach to compute the length of the critical paths is to simulate the combinational circuit for all possible input vectors (vector dependent approach). However, since the number of different input vectors increases exponentially with the number of inputs, this approach is only feasible for to circuits with only a few primary inputs. The first approach to compute the length of the critical paths, without simulating all input vectors (vector independent approach), was based on the PERT (Program Evaluation and Review Technique) algorithm [1]. Since this approach determines the longest path without taking the logical dependencies into account, it is very likely to find a false path. The PERT delay was therefore used as an upper bound for the length of the critical paths. However, the growing complexity and integration of combinational circuits started to demand tighter bounds. This has resulted in different timing analysis (or critical path finding) approaches, each one based on a different path sensitization criterion. The static criterion [2] provides a lower bound, while others [3-6] offer an upper bound. The viability criterion [7] gives the exact delay of the critical paths.