Implementation of Novel Block and Convolutional Encoding Circuit Using FS-GDI

Abstract

A novel implementation of Block and Convolutional encoding circuits approach using Gate Input Diffusion-Full Swing (FS-GDI) and Complementary Metal Oxide Semiconductor (CMOS) logic styles has been presented. Performance analysis of the proposed encoding circuits has been performed using Cadence Virtuoso (CV) S/W package. The performance metrics of FS-GDI-based encoding circuits have been compared with traditional CMOS-based designs. The proposed encoding circuits involve Block Hamming (15, 11), Convolutional (2, 1, 3), and Recursive Systematic Convolutional (2, 1, 2) encoding circuits; these presented circuits are simulated and tested using a word length of 11 bits. The simulation experiments revealed that the proposed implemented circuits achieve delay time improving by 27.91% and 33.27% for Hamming (15, 11) and Convolutional (2, 1, 3) codes, respectively. The simple proposed RSC encoder performs better than the Convolutional (2, 1, 3) due to shorter constraint length and less H/W complexity. On the other hand, the Transistor Count-Hardware (TC-H/W) is enhanced by 50% for the Block and Convolutional encoding based on employing area-efficient FS-GDI-XOR gate. From the analysis of the results, the proposed designs achieve efficient power and delay optimization of Hamming and Convolutional encoding utilizing the FS-GDI logic style. Also, it is clear that the characteristics of the proposed encoding circuits are vital and effective in the digital signal processing circuits and encoding/decoding schemes implementation in low-power wireless networks.