Electrostatic Discharge Performance Research Articles

A False Trigger-Strengthened and Area-Saving Power-Rail Clamp Circuit with High ESD Performance.

A power clamp circuit, which has good immunity to false trigger under fast power-on conditions with a 20 ns rising edge, is proposed in this paper. The proposed circuit has a separate detection component and an on-time control component which enable it to distinguish between electrostatic discharge (ESD) events and fast power-on events. As opposed to other on-time control techniques, instead of large resistors or capacitors, which can cause a large occupation of the layout area, we use a capacitive voltage-biased p-channel MOSFET in the on-time control part of the proposed circuit. The capacitive voltage-biased p-channel MOSFET is in the saturation region after the ESD event is detected, which can serve as a large equivalent resistance (~106 Ω) in the structure. The proposed power clamp circuit offers several advantages compared to the traditional circuit, such as having at least 70% area savings in the trigger circuit area (30% area savings in the whole circuit area), supporting a power supply ramp time as fast as 20 ns, dissipating the ESD energy more cleanly with little residual charge, and recovering faster from false triggers. The rail clamp circuit also offers robust performance in an industry-standard PVT (process, voltage, and temperature) space and has been verified by the simulation results. Showing good performance of human body model (HBM) endurance and high immunity to false trigger, the proposed power clamp circuit has great potential for application in ESD protection.

π-Shape ESD Protection Design for Multi-Gbps High-Speed Circuits in CMOS Technology

CMOS integrated circuits are vulnerable to electrostatic discharge (ESD); therefore, ESD protection circuits are needed. On-chip ESD protection is important for both component-level and system-level ESD protection. In this work, on-chip ESD protection circuits for multi-Gbps high-speed applications are studied. π-shaped ESD protection circuit structures realized by staked diodes with an embedded silicon-controlled rectifier (SCR) and resistor-triggered SCR are proposed. These test circuits are fabricated in CMOS technology, and the proposed designs have been proven to have better ESD robustness and performance in high-speed applications.

Self‐adaptive electrostatic discharge performance of ZnO microvaristors doped silicone rubber composites

AbstractWith the increase in applied voltage and the decrease in volume, integrated electronic modules have become electrostatic sensitive. ZnO microvaristors doped silicone rubber (SiR) composite, with electric field‐dependent conductivity, shows promising prospects for solving the electrostatic problem. In this study, 20 vol% to 50 vol% ZnO/SiR composite films, filled with 10–30 μm ZnO microvaristors, were prepared and put into the test of electrostatic discharge. Compared with the insulating and conducting materials, ZnO/SiR composites achieve the lowest initial voltage and a short time constant of electrostatic discharge. With the increase of ZnO microvaristors volume fraction, from 20% to 50%, the initial voltage and the time constant of electrostatic discharge drop from 1.78 to 0.72 kV and 3.1 ms to 0.4 μs. When the ZnO volume fraction is higher than 30%, there is no residual voltage after 0.1 s. To explore the reason behind different electrostatic discharge performances of the ZnO/SiR composites, the conductivities of the composites were measured. It is found that the break‐over voltage of the composite drops with the increase in the ZnO microvaristors volume fraction. When a high voltage impulse is applied on the ZnO/SiR film, the composite will turn to the conducting state and release the electrostatic charge adaptively so that the initial voltage can be controlled. This work supplies a novel electrostatic discharge idea for electric and electronic devices.

ESD nMOSFETs in Advanced Bulk FinFET Technology With Dual S/D Epitaxy

In this work, the electrostatic discharge (ESD) reliability of the OFF- and ON-state NMOS field-effect transistors in a bulk FinFET technology are investigated. The impacts of source and drain epitaxy influenced by the gate pitch (GP) and the gate length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{g}$ </tex-math></inline-formula> ) are studied. In the OFF-state NMOSFET, which is known as grounded-gate NMOS (ggNMOS), the large GP introduces nonuniform epitaxy on source and drain, which cause high power density localization in device. The large <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{g}$ </tex-math></inline-formula> effectively helps the ESD performance of ggNMOS in ways of better turn-on and contact current uniformity. The ON-state NMOSFET as an active power-rail clamp is also studied in 3-D TCAD simulations. The device shows little difference to transient responses, while the clamping voltage can be different with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{g}$ </tex-math></inline-formula> and GPs. With the same gate space, the short <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{g}$ </tex-math></inline-formula> device has a lower clamping voltage and ON-resistance, which reduces oxide breakdown risk and achieves better ESD performance.

Power Rail ESD Protection Design Methodology Using Voltage-Gain Inverter Based Feedback Technology

In power rail, electrostatic discharge (ESD) is one of the assured issues to be faced. This paper intended to have a voltage gain inverter-based response technology for power rail ESD protection. This paper proposes a power MOSFET to discharge ESD current with 10 ns RC time constant for triggering and transmission gate based clamp is to keep it on until ESD event, which is 28% more efficient than the conventional clamp. The proposed clamp can endure 4500V of HBM (Human Body Model) pulse and also suitable for Charged-Device Model (CDM) protection. Here, LTspice software is used to check out the ESD performance of the transmission gate-based clamp.

Design and optimization of DTSCR for high-speed I/O ESD protection of on-chip ICs

A gate-assisted and diode-triggered silicon controlled rectifier with the waffle layout (GDTSCR-WL) is proposed and investigated. By designing the waffle layout in the conventional diode-triggered silicon controlled rectifier (DTSCR), the electrostatic discharge (ESD) performance of the GDTSCR-WL can be used to optimize remarkably, especially for the parasitic capacitance, clamping voltage (V C), and current handling ability. By further introducing the gate-assisted trigger effect, the GDTSCR-WL can discharge the ESD-induced current more quickly. The technology computer aided design (TCAD) simulations and electrical test results indicate that the GDTSCR-WL has extraordinary ESD performance, such as a V C of 1.24 V, a turn-on resistance of 0.14 Ω, and the large figure of merit of 5.76 mA μm−2, outperforming dual-diode string and DTSCR. Moreover, by adjusting the width W 1 and space W 2 of diode blocks with the waffle layout, the capacitance of the GDTSCR-WL can be continuously decreased from 140 to 92 fF. The optimized GDTSCR-WL with a small capacitance can pass the 8 kV human body model test, providing an efficient and optional solution for high-speed input/output ESD protection of on-chip ICs.

ESD Design Verification Aided by Mixed-Mode Multiple-Stimuli ESD Simulation

Electrostatic discharge (ESD) protection is a grand design challenge for complex ICs in advanced technologies. ESD simulation is indispensable to guide ESD protection designs. However, no existing ESD simulation methods may accurately predict ESD protection designs in a universal manner due to various inherent limitations. TCAD-based ESD simulation is very useful for ESD protection designs. Transmission line pulse (TLP) and very fast TLP (VFTLP) are widely used to evaluate human body model (HBM) and charged device model (CDM) ESD protection designs, which provide rich details for calibrating TCAD ESD simulation for design prediction and validation. Using various ESD protection devices fabricated in 28nm CMOS and 45nm SOI CMOS technologies, a comprehensive experimental and simulation study finds that the ESD stimuli used in TCAD ESD design simulation have profound impacts on many subtle ESD protection behaviors, particularly in comparison with ESD testing. This study cautions against over-interpretation of TCAD ESD simulation results, obtained using any specific ESD stimulus, attempting to accurately predict practical ESD protection designs. A mixed-mode multiple-stimuli ESD simulation method is therefore developed to address the ESD stimulus induced ESD performance variation, hence offering a technique to achieve ESD protection design prediction.

RF/High-Speed I/O ESD Protection: Co-optimizing Strategy Between BEOL Capacitance and HBM Immunity in Advanced CMOS Process

In order to meet the requirement of ultrahigh-speed, low latency, and wide bandwidth (BW) in the next 5G mobile network and internet of things (IoT) applications, the parasitic capacitance specification of electrostatic discharge (ESD) protection devices should become much stricter. Reducing the capacitance always degrades the ESD performance in terms of shrinking the size of the ESD protection device. The distributed ESD protection network is one of the solutions which mitigates the capacitance issue and provides a broadband design. However, while the ESD devices are put under the I/O pad in the distributed ESD protection network, back-end-of-line (BEOL) capacitance starts to play an important role in the advanced 28-nm CMOS process. Therefore, a tapered metal structure is proposed to significantly reduce 30% BEOL capacitance of the ESD device, which can gain a 2.8-GHz increase in the operational BW in the distributed network. Meanwhile, it can enhance the human-body-model (HBM) level up to 16% higher than the original layout style under the same front-end-of-line (FEOL) layout size.

Improvement of electrostatic discharge current-handling capability for high-voltage multi-finger nLDMOS devices with self-triggered technique

The structure of the conventional laterally diffused metal-oxide semiconductor (LDMOS) is modified to be fit for application of a self-triggered technique in multi-fingered high-voltage LDMOS devices to enhance the electrostatic discharge (ESD) current-handling capability. Device simulation and transmission line pulse testing are employed to analyze the working mechanism and ESD performance of the proposed device with self-triggered technique based on a 0.5 µm 24 V CMOS DMOS (CDMOS) process. According to the measurement results, compared to traditional gate-grounded LDMOS, the secondary breakdown current () of the proposed device with low-trigger-voltage triggering finger can be drastically improved from 2.43 A to 5.57 A, and its trigger voltage () is reduced from 59.91 V to 48.18 V.

A Radiation-Hardened Dual-Direction SCR Based on LDMOS for ESD Protection in the Extreme Radiation Environment

To mitigate the total ionizing dose (TID) effects of the dual-direction silicon-controlled rectifier, based on laterally diffused metal–oxide–semiconductor (LDMOS-DDSCR), a common-centroid layout arrangement with multiple octagonal units is proposed and fabricated in an 18-V Bipolar-CMOS-DMOS process. The symmetrical characteristics of the bidirectional electrostatic discharge (ESD) protection are verified by transmission line pulse tests. Gamma-ray irradiation experiments demonstrate that the proposed device is tolerant of TID effects up to 100 krad(Si), whereas the traditional finger-type LDMOS-DDSCR loses its function at 50 krad(Si). Finally, the ESD performance is also characterized at high temperatures which confirms that the proposed device is an excellent candidate for space applications.

Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits—Part II

This article describes a systematic and scalable electrostatic discharge (ESD) verification methodology embodied in a tool called ESD IP Explorer that has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures. The tool identifies the ESD protection network of a circuit thanks to a flexible topology-aware mechanism and converts the circuit description of this network into a directed graph whose edges are provided with quasistatic electrical behaviors inferred from the machine learning techniques detailed in a companion paper. A graph-based analysis establishes a risk rating cartography for all top-level pad-to-pad discharge combinations. The circuit reviewer, a chip designer, or an ESD expert can, therefore, assess the ESD performances of the ESD network under study and easily investigate potential ESD design weaknesses.

Reliability Scaling of Nanoscale Avalanche Photodiodes in High-Speed Optical Communication

In the present era of big data and 5G wireless, both microelectronic and photonic components are indispensable building blocks. For microelectronics, device miniaturization has been following Moore&amp;rsquo;s law to attain higher speed and greater functionality. For photonics, similar device scaling is also evolving in both lasers and photodiodes to transmit high data rates of 25 Gb/s and beyond. However, such device miniaturization may impose challenges such as reliability and fabrication that require careful scientific and engineering studies. In particular, the reliability understanding of photonic device scaling is fairly rudimentary with only scattered reports. In this paper, we study the device and reliability scaling of nanoscale avalanche photodiodes (APDs). The device miniaturization of APDs mainly involves thickness reduction in the charge control and multiplication layers. The layer reduction however causes an increase in breakdown field that may adversely affect reliability in several aspects such as electrical/optical overload and electrostatic discharge (ESD). We present a new reliability degradation model of APDs based on the breakdown field and correlate it with the experimental data. Empirical reliability equations are instituted to establish quantitative formulation. We discuss the overload and ESD performances as a function of breakdown field for both planar-type and mesa-type APD structures.

Designing ESD Protection Devices for Ultrafast Overvoltage Events

This article provides an understanding of the transient voltage overshoot physics observed with electro-static discharge (ESD) n-type, p-type, and n-type diffusions (NPN) bipolar devices through the use of calibrated technical computer-aided design (TCAD) with measured silicon results. This analysis graphically steps through each stage of the measured transient electrical response, to explain the inertia that limits the speed of the NPN ESD cell, and then uses this knowledge to provide a fully characterized silicon solution for ultrafast ESD events to achieve an 8-kV IEC61000-4-4 rating. This solution is developed by exploring five different integrated designs that are constructed on an 80-V bipolar and complimentary double-diffused metal-oxide semiconductor (BiCDMOS) process platform to protect against a product level 125-V voltage overshoot gate oxide ruptures as measured with a 0.6-ns rise time transmission line pulse (TLP). The fully characterized electrical results for each test overshoot structure with a fixed layout area of $200\,\,\mu \text{m}\,\,\times200\,\,\mu \text{m}$ , are in parallel to NPN ESD cells arranged with two in series and two in parallel ( $200\,\,\mu \text{m}\,\,\times 80\,\,\mu \text{m}$ ) and compared in terms of the current-carrying capability before the gate oxide rupture voltage of 125 V is reached. The results show that a diode engineered with a vertical breakdown achieves an ESD strength of 9.7 A before the overshoot voltage reaches the target of 125-V, resulting in a net 0.17 mA $\mu \text{m}^{-{2}}$ . The combined use of this vertical diode structure in parallel to the NPN ESD cell translates into a 7-A improvement in the strength of a conventional NPN for ultrafast timescales, which achieves the 8-kV International Electrotechnical Commission (IEC) ESD performance for this case study.

A compact LDMOS DDSCR for HV ESD protections with high robustness and reliability

The LDMOS-based silicon controlled rectifier (SCR) is commonly used in high voltage (HV) electrostatic discharge (ESD) protection due to its great current handling capability per area and HV protection ability. In this paper, an improved LDMOS-based dual direction SCR (LDMOS-DDSCR) device is designed by replacing floating N+ region with electrically-connected P+, N+ and P+ regions to enhance its ESD robustness, which is verified in a 0.5-μm (1p2m) 18 V HV CDMOS process. The internal mechanism of the proposed device is analyzed using two-dimension (2D) TCAD simulations, and the ESD performance is characterized by means of transmission line pulse (TLP) and very-fast TLP (VFTLP) measurements. Compared with the conventional LDMOS-DDSCR, the failure current of the compact LDMOS-DDSCR raises from 2.00 A to 4.02 A (increased by 101%), and the trigger voltage reduces from 44.28 V to 39.76 V, without sacrificing layout area. Furthermore, the TLP I-V curves of the proposed LDMOS-DDSCR are measured at different temperatures ranging from 25 °C to 125 °C, which proves its reliability and show potential use in the applications of high voltage integrated circuits.

A 6.5-kV HBM ESD-protected high-gain LNA using cascaded L-match input network

A wideband (2–3 GHz) three-stage low noise amplifier (LNA) with electrostatic discharge (ESD) protection circuits using 0.18 [Formula: see text]m CMOS technology is presented in this paper. Low-parasitic silicon-controlled rectifier (SCR) devices are co-designed with the LNA in the form of [Formula: see text]-parameters, and a new cascaded L-match input network is proposed to reduce the parasitic effects of them on the input matching. To improve linearity performance, an optimized multiple-gated transistors method (MGTR) is proposed and applied to the third stage, which takes both transconductance [Formula: see text] and third-order nonlinear coefficient [Formula: see text] into consideration. The measured results show a wide input matching across 2–8 GHz and a high third-order input intercept point (IIP3) of −12.8 dBm. The peak power gain can achieve 29.1 dB, and the noise figure (NF) is in a range of 3.1–3.6 dB within the 3-dB bandwidth. Using SCR devices with low parasitic capacitance of [Formula: see text]80 fF and robust gate-driven power clamps, a 6.5-kV human body mode (HBM) ESD performance is obtained.

Improving robustness of GGNMOS with P-base layer for electrostatic discharge protection in 0.5- BCD process

Gate-grounded N-channel MOSFET (GGNMOS) has been extensively used for on-chip electrostatic discharge (ESD) protection. However, the ESD performance of the conventional GGNMOS is significantly degraded by the current crowding effect. In this paper, an enhanced GGNMOS with P-base layer (PB-NMOS) are proposed to improve the ESD robustness in BCD process without the increase in layout area or additional layer. TCAD simulations are carried out to explain the underlying mechanisms of that utilizing the P-base layer can effectively restrain the current crowing effect in proposed devices. All devices are fabricated in a 0.5- BCD process and measured using the transmission line pulsing (TLP) tester. Compared with the conventional GGNMOS, the proposed PB-NMOS devices offer a higher failure current than its conventional counterpart, which can be increased by 15.38%. Furthermore, the PB-NMOS_type3 possesses a considerably lower trigger voltage than the conventional GGNMOS to protect core circuit effectively.

Facile and cost-effective strategy for fabrication of polyamide 6 wrapped multi-walled carbon nanotube via anionic melt polymerization of ε-caprolactam

There is a growing demand for the development of a melt process-based nanocomposite manufacturing process capable of minimizing the incorporation of expensive carbon nanotubes (CNTs) by inducing a uniform dispersion of multi-walled CNTs (MWNTs). In this study, we proposed a nanocomposite manufacturing process that includes both physical particle mixing using high-speed rotation and anionic polymerization of ε-caprolactam (CL) to induce a uniform dispersion of MWNTs. MWNTs were uniformly dispersed by powder mixing and then wrapped with polyamide 6 polymers by in-situ polymerization of CL. The synergistic effect of the two sub-processes resulted in an enhanced dispersion of MWNTs and prevented aggregation of the MWNTs. The composites fabricated by the proposed process exhibited electrical conductivities of 4.49 × 10−5 S/m and 1.45 × 10 S/m at 1 wt% and 3 wt% MWNTs, respectively, indicating that by applying the proposed process it is possible to incorporate a smaller amount of MWNT to achieve electrical conductivities applicable for electrostatic discharge (ESD) (>1 X 10−5 S/m) and electromagnetic interference shielding effectiveness (EMI SE) (>10 S/m) applications. An ESD chip tray and EMI SE mobile phone case were fabricated using the prepared composite, and it was verified that the ESD and EMI SE performances can be realized.

Gate-Lifted nMOS ESD Protection Device Triggered by a p-n-p in Series With a Diode

We demonstrate a gate-lifted nMOS electrostatic discharge (ESD) protection device triggered by a p-n-p in series with a diode in a 0.18- $\mu \text{m}$ bulk CMOS technology for 5-V mobile applications up to 85 °C. This voltage-triggering scheme is suitable for fail-safe, open-drain, supply, and surge protections. In addition, the robust ESD performance is boosted by parasitic embedded-silicon-controlled-rectifier action in the high-current regime. No extra masks nor additional RC control circuitry are required for this implementation.

On the ESD Behavior of Large-Area CVD Graphene Transistors: Physical Insights and Technology Implications

In this paper, for the first time, the record high-performance top-gated graphene technology platform is used for electrostatic discharge (ESD) physics exploration while investigating the implications of various design and technology options. Impact of diffusive versus ballistic carrier transport on the failure mechanism in top-gate as well as back-gate graphene FET (GFET) is investigated. A unique contact limited failure in graphene transistors is reported. Physical insights on current saturation in GFET and unique step-by-step failure in dielectric capped transistors are presented for the first time. Moreover, device degradation under ESD timescales and its implications on current saturation are revealed. Finally, the influence of various top-gate designs on the ESD performance is reported. New physical insights and matured GFET technology has eventually enabled record high ESD robustness.

Investigation of layout effects in diode-triggered SCRs under very-fast TLP stress through full-size, calibrated 3D TCAD simulation

Electrostatic discharge (ESD) protection devices in advanced state-of-the-art CMOS technologies need to be optimized towards minimizing size and capacitive loading of the core circuitry without loss of ESD performance. In this work, a layout study of diode-trigged SCR (DTSCR) by means of calibrated 3D TCAD is presented. The focus lies on layout dependent uniformity of operation, and transient turn-on behaviour under very-fast (vf)-TLP stress, for which a 3D approach is mandatory. In this context, we employ a novel TCAD methodology that allows to reliably perform 3D process simulations in a fast, and yet accurate way. We can generate very large device structures with a mesh node count in the order of millions, such as the DTSCRs under investigation. Using rigorous 3D process simulation would be too expensive, or simply not feasible. Process simulation turnaround time (TAT) reduction from weeks to days or hours opens for the possibility of using the 3D TCAD simulation deck for guiding the layout optimization process.