Investigation of layout effects in diode-triggered SCRs under very-fast TLP stress through full-size, calibrated 3D TCAD simulation

Abstract

Electrostatic discharge (ESD) protection devices in advanced state-of-the-art CMOS technologies need to be optimized towards minimizing size and capacitive loading of the core circuitry without loss of ESD performance. In this work, a layout study of diode-trigged SCR (DTSCR) by means of calibrated 3D TCAD is presented. The focus lies on layout dependent uniformity of operation, and transient turn-on behaviour under very-fast (vf)-TLP stress, for which a 3D approach is mandatory. In this context, we employ a novel TCAD methodology that allows to reliably perform 3D process simulations in a fast, and yet accurate way. We can generate very large device structures with a mesh node count in the order of millions, such as the DTSCRs under investigation. Using rigorous 3D process simulation would be too expensive, or simply not feasible. Process simulation turnaround time (TAT) reduction from weeks to days or hours opens for the possibility of using the 3D TCAD simulation deck for guiding the layout optimization process.