On the ESD Behavior of Large-Area CVD Graphene Transistors: Physical Insights and Technology Implications

Abstract

In this paper, for the first time, the record high-performance top-gated graphene technology platform is used for electrostatic discharge (ESD) physics exploration while investigating the implications of various design and technology options. Impact of diffusive versus ballistic carrier transport on the failure mechanism in top-gate as well as back-gate graphene FET (GFET) is investigated. A unique contact limited failure in graphene transistors is reported. Physical insights on current saturation in GFET and unique step-by-step failure in dielectric capped transistors are presented for the first time. Moreover, device degradation under ESD timescales and its implications on current saturation are revealed. Finally, the influence of various top-gate designs on the ESD performance is reported. New physical insights and matured GFET technology has eventually enabled record high ESD robustness.