Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits—Part II

Abstract

This article describes a systematic and scalable electrostatic discharge (ESD) verification methodology embodied in a tool called ESD IP Explorer that has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures. The tool identifies the ESD protection network of a circuit thanks to a flexible topology-aware mechanism and converts the circuit description of this network into a directed graph whose edges are provided with quasistatic electrical behaviors inferred from the machine learning techniques detailed in a companion paper. A graph-based analysis establishes a risk rating cartography for all top-level pad-to-pad discharge combinations. The circuit reviewer, a chip designer, or an ESD expert can, therefore, assess the ESD performances of the ESD network under study and easily investigate potential ESD design weaknesses.