Hot Carrier Injection Effect Research Articles

Reliability-aware design of Integrate-and-Fire silicon neurons

Variation in CMOS device parameters due to reliability issues like Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI), etc., has posed serious performance concerns in various digital and analog/mixed-signal circuit designs, which include neuromorphic circuits. CMOS-based neuromorphic circuits, also known as silicon neurons (SiNs), are designed to emulate the electrophysiological behavior of biological neurons. Neuromorphic systems are used to learn and adapt in various applications like image processing and classification, wearable/implantable systems, robotics, etc. that require high performance. It is therefore, important to analyze neuromorphic circuits performance over their lifetime. This is achieved by identifying the specific transistors affecting circuit performance and to come up with workable ways to solve these problems. In this work, we have investigated the combined effect of NBTI and HCI on two types of Integrate-and-Fire (I&F) SiNs, Axon-Hillock (AH) and Simplified Leaky Integrate-and-Fire (SLIF) circuits, using key performance parameters. Novel reliability-aware AH and SLIF circuits are proposed to mitigate the reliability issues. The proposed reliability-aware designs show negligible deviations in the performance parameters after degradation. The time-zero process variability analysis is also carried out for the proposed reliability-aware SiNs. The power consumption of existing and proposed reliability-aware neuron circuits is analyzed and compared.

A HCI-hardened self-healing operational amplifier circuit

In this paper, a self-healing operational amplifier circuit to deal with hot carrier injection (HCI) effect is proposed. An inverter-based operational amplifier is implemented. The influence degree of HCI effect to performance of the operational amplifier is studied which utilizes an equivalent circuit model of HCI effect. A monitoring circuit is proposed to monitor the degree of HCI degradation. A charge pump circuit is utilized to generate a corresponding voltage according to the result of monitoring circuit. The output voltage of the charge pump circuit is feedback to tune the substrate voltage of the operational amplifier (and the monitoring circuit) to mitigate degradation. The simulation results show that the self-healing operational amplifier can maintain the performance at low temperature and room temperature for 50 years (and high temperature for 30 year) under HCI effect. The gain of the inverter-based operational amplifier without self-healing is reduced from 45 dB to 9.6 dB after 50 years, and the gain of the self-healing operational amplifier will maintain at about 46 dB among 50 years. The influence of HCI effect on bandwidth and phase margin is less than that of temperature and process corner. The lifetime of self-healing operational amplifier circuit is >5 times longer than lifetime of based on inverter operational amplifier circuit without self-healing. In addition, the self-healing operational amplifier is robust to process corner.

Recovery Effect of Hot-Carrier Stress on γ-ray-Irradiated 0.13 μm Partially Depleted SOI n-MOSFETs

Many silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) are used in deep space detection systems because they have higher radiation resistance than bulk silicon devices. However, SOI devices have to face the double challenge of radiation and conventional reliability problems, such as hot carrier stress, at the same time. Thus, we wondered whether there is any interaction between reliability degradation and irradiation damage. In this paper, the effect of hot-carrier injection (HCI) on γ-ray-irradiated partially depleted (PD) SOI n-MOSFETs with a T-shaped gate structure is investigated. A strange phenomenon that accelerated the annealing effect on irradiation devices caused by HCI in 5 s was observed. That is, HCI has fast recovery ability on the irradiated narrow-channel n-MOSFETs. We explain the physical mechanism of this recovery effect qualitatively. Moreover, we designed a comparable experiment to evaluate the effect on the wide-channel devices. These results show that the narrow-channel devices are more sensitive to irradiation and HCI effects than wide-channel devices.

A HCI self-healing circuit of a bandgap reference circuit with curvature compensation

In this paper, the performance degradation of a bandgap reference circuit with curvature compensation under the hot carrier injection (HCI) effect is studied, and a self-healing circuit is proposed. The intrinsic performance of the curvature compensation bandgap circuit achieved a temperature coefficient (TC) of 1.949 ppm/°C and an output reference voltage of 384.748 mV under a 1.2 V power supply voltage between −40 °C to 125 °C. The TC of the reference circuit will increase to 8.033 ppm/°C and the output reference voltage decreases to 384.318 mV after 50 years under the HCI effect. The study found that the gain decrease of the op-amp in the reference circuit leads to a decrease in the output voltage, and the decrease of the compensation current in the curvature compensation circuit leads to the degradation of the TC. A self-healing circuit is designed to mitigate the impact of the HCI effect. The simulation results show that the TC of the self-healing reference circuit is 3.934 ppm/°C and the output reference voltage is 384.655 mV after 50 years under the HCI effect.

An equivalent circuit model of HCI effect for short-channel N-MOSFET

The hot carrier injection (HCI) effect is an essential factor for the reliability of N-MOSFET. Under long-term usage time, the HCI effect will affect the threshold voltage, transconductance, saturation drain-source current of N-MOSFET, etc. It will seriously affect the performance and lifetime of products. The current model for HCI effect simulation is mainly by modifying the SPICE model of N-MOSFET, which requires complex experiments and parameter extraction. This paper establishes an HCI effect equivalent circuit model for a 65 nm N-MOSFET. Based on the N-MOSFET model in a 65 nm Process Design Kit (PDK), essential electrical components and arithmetic components (which are provided by EDA tools), this equivalent circuit model achieves the HCI effect simulation. This equivalent circuit model offers five tunable input parameters for the user, which are channel width (W), channel length (L), ambient temperature (Temp), stress time (Year), process corner (fast, typical, slow). The effect of gate-source voltage, drain-source voltage, and gate-drain voltage on HCI effect is included in this model. The simulation results of this model are compared with the measured results in other literatures, and the results are fitted well.

Modelling and Failure Analysis of SiC MOSFET under the Effects of Parasitic Parameters

Recent years, SiC MOSFET has been gradually utilized in high power devices. However, it has become one of the highest failure rate devices in circuit systems. Its failure relates to the degradation which caused by the hot carrier injection(HCI) effect. Because the parasitic parameters make the oscillations in switching processes more intense, the switching time and voltage overshoot increases, and thus HCI effect exacerbates. So, it is necessary to analyse the influence of parasitic parameters on the failure of SiC MOSFET. In this paper, an improved SiC MOSFET model with all key parasitic parameters is built to set up an accurate test circuit. The parasitic parameters were divided into four parts: body diode, parasitic resistance, parasitic capacitance and parasitic inductance. According to the simulation, it concluded that only the parasitic inductance has a great impact on the HCI effect and the impacts are different according to the different locations of parasitic inductance. The influence of the parasitic inductance on the load circuit and near the source is much greater than other parts. Their increase greatly increases switching time and voltage overshoot, and thus exacerbates HCI effect and accelerates the degradation of SiC MOSFET.

The influence of total ionizing dose on the hot carrier injection of 22 nm bulk nFinFET

We investigate the hot carrier injection effect (HCI) and how X-ray radiation impacts the HCI of 22-nm nFinFETs as a function of device geometry and irradiation bias conditions in this paper. In the HCI test, the degradation of threshold voltage and saturation current decreases with the increase of fin number, which means that HCI weakens when the fin number increases. The reason is attributed to the coupling effect between fins. Moreover, irradiation is shown to weaken the degradation during the subsequent hot carrier test. The influence of irradiation on HCI is more obvious with ON bias than that of OFF bias and transmission gate bias. It is supposed that the Si–H bonds can be broken by irradiation before the HCI test, which is one reason for the irradiation influence on HCI. Besides, trapped charges are generated in the shallow trench isolation by the radiation, which could reduce the channel electric field, and then weaken the HCI.

Research for Hot Carrier Degradation in N-Type Bulk FinFETs

In this paper, the effect of hot carrier injection on an n-bulk fin field-effect transistor (FinFET) is analyzed. The hot carrier injection method is applied to determine the performance change after injection in two ways, channel hot electron (CHE) and drain avalanche hot carrier (DAHC), which have the greatest effect at room temperature. The optimum condition for CHE injection is VG=VD, and the optimal condition for DAHC injection can be indirectly confirmed by measuring the peak value of the substrate current. Deterioration by DAHC injection affects not only hot electrons formed by impact ionization, but also hot holes, which has a greater impact on reliability than CHE. Further, we test the amount of drain voltage that can be withstood, and extracted the lifetime of the device. Under CHE injection conditions, the drain voltage was able to maintain a lifetime of more than 10 years at a maximum of 1.25 V, while DAHC was able to achieve a lifetime exceeding 10 years at a 1.05-V drain voltage, which is 0.2 V lower than that of CHE injection conditions.

SRAM Stability Analysis and Performance–Reliability Tradeoff for Different Cache Configurations

Bias temperature instability (BTI), hot carrier injection (HCI), gate-oxide time-dependent dielectric breakdown (GTDDB), and random telegraph noise (RTN) degrade the stability of the deeply scaled transistors and the overall circuit reliability. These front-end wearout mechanisms are especially acute in the static random access memory (SRAM) cells of first-level (L1) caches, which are crucial for the performance of microprocessors due to frequent accesses. This article presents a methodology to analyze cache reliability degradation due to the combined effect of BTI, HCI, GTDDB, and RTN for different cache configurations, including variations due to associativity, cache line size, cache size, and the error-correcting codes (ECCs). Time-zero variability due to process and environmental parameters are also considered. First, we analyze how each wearout mechanism affects reliability degradation. Then we analyze the relationship between reliability (probability of failure) and performance (hit rate) of the L1 cache within a LEON3 microprocessor, while the LEON3 is running a set of benchmarks, which determine cell array activity, characterized by the duty cycle, toggle rate, temperature, and supply voltage distributions of cells. Insights on the performance-reliability tradeoff are provided for cache designers.

Total-ionizing-dose induced enhanced hot-carrier injection effect in the 130 nm partially depleted SOI I/O nMOSFETs

An enhanced threshold shift was observed in irradiated (total-ionizing-dose) 130 nm partially depleted silicon-on-insulator I/O nMOSFETs after 3000 s channel hot-carrier stress. This phenomenon was caused by the irradiation-induced additional channel lucky electrons which were injected in the silicon dioxide layers (STI/BOX/gate oxide). Mechanism of formation of greater substrate current in irradiated narrow devices was discussed. Accordingly, a model (enhanced lucky-electron model/Hot carrier injection effect) applied to devices in radiation space environment is established. In addition, the unusual phenomenon in irradiated devices with wide channel was also discussed.

Device Reliability Challenges in Advanced FinFET Technology

Abstract This article discusses the effect of hot carrier injection, bias temperature instability, and time-dependent dielectric breakdown on FinFET performance and reliability.

Impact of Aging on the Reliability of Delay PUFs

Physically Unclonable Functions (PUFs) are mainly used for generating unique keys to identify electronic devices. These entities mainly benefit from the process variations occurring during the device manufacturing. To be able to use PUFs to identify electronic devices or to utilize them in cryptographic applications, the reliability of PUFs needs to be assured under a wide variety of environmental conditions and aging mechanisms, including the switching activity of the PUFs’ internal signals. In practice, it is important to evaluate aging effects as early as possible, preferentially at design time. In this paper, we evaluate the impact of aging on two types of delay-PUFs (arbiter-PUFs and loop-PUFs) with different switching activities. This work takes advantage of both simulation tool and silicon tests on a 65nm ASIC implementation. To expedite the simulation process and get rid of conducting simulations of multiple delay-element PUFs, we propose an extrapolation method to evaluate the effect of BTI (Bias Temperature-Instability) and HCI (Hot Carrier Injection) aging under different switching activities on PUFs with multiple delay elements using the aging effects on single delay-element PUFs. The results show that switching activity (expressed in terms of transitions/time) has a limited impact on delay chains of considered delay-PUFs, while it has a greater impact on the arbiter (RS latch) of the arbiter-PUF. The simulation results show that the aging-related Bit Error Rate in an arbiter-PUF with high switching activity can be 11 times worse than the Bit Error Rate in the same PUF when there is no activity in 20 months.

Effect of hot carrier stress on device junctions measured by electron holography and scanning capacitance microscopy

The effect of hot carrier injection on the FET's junction properties has been investigated for CMOS NFET devices. Junction profiles and carrier concentration of stressed and unstressed devices are measured and compared by dual lens electron holography and scanning capacitance microscopy, respectively. The measurements reveal that the width of the junction on the drain side of the device that undergoes hot carrier stressing decreases, indicating a reduction in active carrier concentration. These results are consistent with the hypothesis of phosphorous dopant passivation by the hot carrier induced release of hydrogen into the drain side extension region.

Role of SiOxNy surface passivation layer on stability improvement and kink effect reduction of ELA poly silicon thin film transistors

The role of SiOxNy thin layer growth on excimer laser annealed (ELA) polysilicon, by N2O plasma treatment, on the stability improvement under prolonged operation and bias stress of TFT was investigated. After NH3 plasma treatment, field effect mobility in p-channel TFT devices increased from 50 to 76cm2V−1s−1, ON/OFF current ratio improved to 4.6×107, threshold voltage shrank from −9.8V to −7.7V and kink effect in the ID-VD characteristics was diminished. Using NH3 plasma treatment combined with SiOxNy layer indicated a lesser effectiveness in decreasing interface states, but better in reducing of the influence of mobile charges on TFT performance, than the previous approaches. An improvement in field effect mobility of 60.5cm2V−1s−1, excellent stability under bias stress of ±1MV·cm−1 for 2h with ΔVth~0.1V were achieved. We found that under NH3 plasma treatment combined with SiNxOy thin layer; the effect of hot carrier injection were reduced significantly due to creating the SiN, and SiO bonding at the interface of gate insulator and active layer. This result indicated that thin film transistor using NH3 plasma treatment with SiOxNy passivated layer promises to improve TFT performances with high field effect mobility, high ON/OFF current ratio, low leakage current and excellent stability.

Total dose dependence of hot carrier injection effect in the n-channel metal oxide semiconductor devices

The equipment and devices which are long-time running in space are affected by space radiation effects and hot carrier injection effects at the same time which would reduce their optional times. Normally, the single mechanism test simulation method is used on the ground simulation test but the multi-mechanism effect affects the space equipments and devices, including total irradiation dose effect, hot carrier injection effect, etc. The total dose dependence of hot carrier injection (HCI) effect in the 0.35 m n-channel metal oxide. semiconductor (NMOS) device is studied in this paper. Three samples are tested under different conditions (sample 1# with total irradiation dose (TID) and HCI test, sample 2# with TID, annealing and HCI test, sample 3# only with HCI test). The results show that threshold voltage of NMOS device with 5000 s HCI test after 100 krad (Si) total dose radiation has been negatively shifted then positively during total dose irradiation test and HCI test, and the threshold is higher than that of the device without radiation test. But the threshold voltage shift of NMOS device with 5000 s HCI test and 200 h annealing test after TID test is higher than that of the devices without radiation test and lower than that of the devices without annealing test. That is, the parameters of NMOS device vary faster with the combined effects (including the total dose irradiation effect and HCI effect) than with single mechanism effect. It is indicated that the hot electrons are trapped by the oxide trap charges induced by irradiation effect and then become a recombination centre. And then the oxide trap charges induced by irradiation effect reduce and become negative electronic. The interface trap charges induced by irradiation effect are reduced and then increased it is because the electrons of hole-electron pairs in the Si-SiO2 interface are recombined by oxide traps in the oxide during the forepart of HCI test but then the electrons are trapped by interface traps in the Si-SiO2 interface because the electrons from source area are injected to interface during the HCI test. So the threshold voltage is positively shifted due to the negative oxide trap charges and interface trap charges. The association effect is attributed to the reduction of oxide traps induced by recombination with hot electrons and the increase of the interface traps induced by irradiation trapped hot electrons.

Gate Engineering in SOI LDMOS for Device Reliability

A linearly graded doping drift region with step gate structure, used for improvement of reduced surface field (RESURF) SOI LDMOS transistor performance has been simulated with 0.35µm technology in this paper. The proposed device has one poly gate and double metal gate arranged in a stepped manner, from channel to drift region. The first gate uses n+ poly (near source) where as other two gates of aluminium. The first gate with thin gate oxide has good control over the channel charge. The third gate with thick gate oxide at drift region reduce gate to drain capacitance. The arrangement of second and third gates in a stepped manner in drift region spreads the electric field uniformly. Using two dimensional device simulations, the proposed SOI LDMOS is compared with conventional structure and the extended metal structure. We demonstrate that the proposed device exhibits significant enhancement in linearity, breakdown voltage, on-resistance and HCI. Double metal gate reduces the impact ionization area which helps to improve the Hot Carrier Injection effect..

Impact of hot carrier injection on switching time evolution for power RF LDMOS after accelerated tests

This paper investigates the effects of hot carrier injection on the switching performance of power RF LDMOS (Radio Frequency Lateral Diffused Metal–Oxide–Semiconductor) devices. In addition, their influences on the dynamic parameters are studied after various accelerated aging tests (thermal and electrical). The response of these parameters and the switching waveform are described. The findings of experimental results are presented and discussed. Measurements show that important variations are obtained on the devices' rise time. After aging tests, the charge trapping in the gate oxide causes the modifications in the Miller capacity level and width resulting in an increase of the rise time and a decrease in the fall time, consequently increasing of the switching losses.

Suppression of Read Disturb Fail Caused by Boosting Hot Carrier Injection Effect for 3-D Stack NAND Flash Memories

A new bias pulse method was proposed to suppress read disturbance in unselected strings of 3-D stack NAND flash memories. Using the proposed read method, we could suppress effectively a large cell Vth shift generated by boosting hot carrier injection. As a result, the cell Vth shift in unselected string is quite similar to normal read disturbance in select string. The proposed read method was verified by both measurement and simulation.

Prediction of energy change due to hot carrier injection in nano-structured CMOS system: Perspective of an envelope detector

Due to aggressive scaling of CMOS technology, many time-variant issues are catastrophic to MOSFET reliability. Hot carrier injection (HCI) is one of these reliability issues and is a limiting factor for n-MOSFET performance. The HCI aging effect causes shift in drain current and threshold voltage at sub-nanometer technologies. There are many works describing device level HCI prediction, but there is still room for improvement in predicting the gain change behavior due to HCI at circuit level. Therefore, we developed a correlation technique to obtain radio frequency and gain change relationship after the HCI effect is induced in a CMOS circuit. In brief, it is a technique to predict the behavior of HCI driven gain transformation with respect to frequency. Therefore, at a certain frequency the change of gain due to HCI can be observed. To implement this technique, we employed an envelope detector circuit and predicted the gain change due to HCI on several technology nodes. Unlike some of the previous prediction techniques, this technique provides a thorough picture of the HCI driven gain change at various frequencies in CMOS circuit. This technique is scalable, as shown by its application to different technology nodes.

A New BSIM3v3 SPICE Model for Reliability of Hot Carrier Injection Effect in MOSFET

This paper reports a new BSIM3v3 SPICE reliability model for describing the reliability of hot carrier injection (HCI) in MOSFET, which can be widely used in traditional process MOSFET. In this work, thousands of BSIM3v3 model parameters are analyzed, seven parameters primarily affected by HCI are extracted and optimized in original BSIM3v3 source code.The I-V simulation results after parameter extraction fits the measured results very well, so an accurate new model of MOSFETs reliability model is achieved. Using the new BSIM3v3 SPICE reliability model, the idvd curves at the stress time from 10 to 50000s of the nMOSFET with 10µm gate length and 0.5µm gate width can be achieved. So the device characters variation with time can be monitored. Besides, the typical Idsat, Vth, Idlin and Gmax degradation as a function of stress time are also plotted and the lifetime of MOSFETs can be evaluated from these functions.