Abstract
A linearly graded doping drift region with step gate structure, used for improvement of reduced surface field (RESURF) SOI LDMOS transistor performance has been simulated with 0.35µm technology in this paper. The proposed device has one poly gate and double metal gate arranged in a stepped manner, from channel to drift region. The first gate uses n+ poly (near source) where as other two gates of aluminium. The first gate with thin gate oxide has good control over the channel charge. The third gate with thick gate oxide at drift region reduce gate to drain capacitance. The arrangement of second and third gates in a stepped manner in drift region spreads the electric field uniformly. Using two dimensional device simulations, the proposed SOI LDMOS is compared with conventional structure and the extended metal structure. We demonstrate that the proposed device exhibits significant enhancement in linearity, breakdown voltage, on-resistance and HCI. Double metal gate reduces the impact ionization area which helps to improve the Hot Carrier Injection effect..
Highlights
Double diffused metal oxide semi-conductor (LDMOS) on SOI substrate is a promising technology for smart power transistors
In SOI Laterally double diffused metal oxide semi-conductor (LDMOS) the kink appearing in the output characteristics
We developed a new innovative n-channel LDMOS device with P-top in the drift region
Summary
Double diffused metal oxide semi-conductor (LDMOS) on SOI substrate is a promising technology for smart power transistors. In the recent past, developing high voltage SOI LDMOS has gained importance due to possibility of its integration with low power devices and heterogeneous microsystem. In SOI LDMOS the kink appearing in the output characteristics. The motivation of this work is to explore structural modification in SOI LDMOS to enhance its high voltage capabilities and ruggedness of the device. The buried oxide in the SOI structure reduces capacitive coupling to the substrate, which improves power efficiency. The SOI buried oxide provide improved isolation between adjacent circuits, making attractive for highly integrated power amplifiers in which substrate cross talks is a concern. A third advantage is that it allows for the use of high resistivity substrates that enable the fabrication of low loss on-chip inductors
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