A Novel Low On-Resistance SOI LDMOS with Double Trench Gates and Plates

Abstract

A novel SOI LDMOS with Double Trench Gate (DTG) is proposed. The DTG SOI LDMOS is obtained by introducing an additional trench gate between P-well region and N- drift region, which can form one more n-channel in on-state. The parameters of DTG SOI LDMOS were optimized to some extend through 2D device simulations and some main electronic properties were obtained through 2D device simulation with Silvaco TCAD and analyzed. The simulation results indicate that the proposed DTG SOI LDMS is featured of lower on-resistance, higher transconductance and higher handle capability of current than those of conventional STG SOI LDMOS. The on-resistance is decreased due to enhancement of electron injection into n-drift region of DTG SOI LDMOS, which further boosts the conductivity modulation effect. Moreover, to increase the thickness of the bottom-wall and sidewall oxide of the additional trench gate can improve the breakdown voltage of the proposed DTG SOI LDMOS in off-state. Consequently, by comparing with Single Trench Gate SOI LDMOS, the breakdown voltage of the proposed DTG SOI LDMOS is increased by 7.0% , its specific on-resistance is decreased about 50% and its transconductance is increased one time more.