Back-gate Effect Research Articles

Growth of large-area two-dimensional non-layered β-In2S3 continuous thin films and application for photodetector device

In this work, the large-area two-dimensional non-layered β-In2S3 continuous thin films were grown on mica substrate by physical vapor deposition (PVD) at temperature of 980 °C using In2S3 powders as precursor. The 2D β-In2S3 thin films were transferred from mica substrate to SiO2/Si substrate. The back-gate field effect transistors (FETs) based on the 2D β-In2S3 thin films were fabricated using a conventional photolithographic technique. The morphology, thickness, crystal structure and optical property of the 2D β-In2S3 thin films as well as photoresponse performance of devices were characterized at room temperature under ambient condition. The results show that the 2D β-In2S3 continuous thin films are assembled from the 2D β-In2S3 flakes by tiling on each other with broad-area plane-to-plane contacts. The thickness of the 2D β-In2S3 films is in the range from 23 to 236 nm. The as-fabricated photodetectors exhibit highly stable and reproducible photoresponse properties with responsivity of 11.2 A/W and external quantum efficiency of 2.6 × 103% under 532 nm incident light with power density of 159.2 mW/cm2. The rise time and decay time of device are 90 ms and 80 ms, respectively. The 2D β-In2S3 thin films have very good application prospects in the field of electronic and optoelectronic devices.

Investigation of DC, RF and linearity performances of a back-gated (BG) heterojunction (HJ) TFET-on-selbox-substrate (STFET): Introduction to a BG-HJ-STEFT based CMOS inverter

This manuscript reports the back-gate effects on device-level performance of a heterojunction TFET on SELBOX substrate (HJ-STFET). The proposed structure implements a stacked gate oxide where the conventional SiO2 is replaced by a SiO2/HfO2 in a stacked manner to increase its On-current. A back gate (BG) is also considered in the proposed TFET to enhance the device-level performance. Investigation of DC, RF and linearity parameters such as drain current, transconductance, electric field, parasitic capacitance, cut-off frequency (fT), gain bandwidth product (GBP), intrinsic delay (ꞇ), higher-order of gm (gm2, gm3), VIP2, VIP3, IIP3, IMD3, and 1-dB compression point are carried out for the proposed TFET and the results are compared with other conventional structures. Performance evaluation shows that BG-HJ-STFET is a suitable candidate for distortionless and high-frequency applications. In addition, analysis of DC and transient behaviour of a CMOS TFET inverter using the BG-HJ-STFET is thoroughly investigated to verify its circuit-level performance.

Nanotip Contacts for Electric Transport and Field Emission Characterization of Ultrathin MoS2 Flakes.

We report a facile approach based on piezoelectric-driven nanotips inside a scanning electron microscope to contact and electrically characterize ultrathin MoS2 (molybdenum disulfide) flakes on a SiO2/Si (silicon dioxide/silicon) substrate. We apply such a method to analyze the electric transport and field emission properties of chemical vapor deposition-synthesized monolayer MoS2, used as the channel of back-gate field effect transistors. We study the effects of the gate-voltage range and sweeping time on the channel current and on its hysteretic behavior. We observe that the conduction of the MoS2 channel is affected by trap states. Moreover, we report a gate-controlled field emission current from the edge part of the MoS2 flake, evidencing a field enhancement factor of approximately and a turn-on field of approximately at a cathode–anode separation distance of .

Fabrication and characteristics of back-gate black phosphorus effect field transistors based on PET flexible substrate

Black phosphorus (BP) is a layered material that is stacked together between independent atomic layers by internal van der Waals forces. In this study, we qualitatively found that the peak value of BP film with different thickness under the AFM characterization would increase with the increase of thickness, and the friction ring had a tendency of expansion. The characteristic peak within a certain range under Raman characterization will redshift with the increase of thickness, and the redshift will weaken with the continuous increase of thickness. These efforts provide the basis for selecting a suitable BP film material as the semiconductor channel for the transistor. The output characteristics and transfer characteristics of the back-gate BP field effect transistor (FET) based on PET flexible substrate are also investigated in detail. A back-gate BP FET based on a PET flexible substrate exhibits a transistor characteristic of a p-type doped ohmic contact in an output characteristic. In the transfer characteristics, the hole mobility of the back-gate BP FET device based on the PET flexible substrate was 266.6 cm2v−1 s−1 and electron mobility was 3.5 cm2v−1 s−1, and the hole mobility was 75 times that of the electron. It has a switch ratio exceeding 8.6 × 103 at the hole end. Experimental results show that the electrical properties of the device show good Schottky diode characteristics. The back-gate BP FET based on PET flexible substrate has good performance and low cost, which adds to the research and application of nano-transistor, and also contributes to the development of flexible electronic equipment.

Overflow Handling Integrate-and-Fire Silicon-on-Insulator Neuron Circuit Incorporating a Schmitt Trigger Implemented by Back-Gate Effect.

In this research, we propose an Integrate-and-fire (I&F) Silicon-on-insulator (SOI) neuron circuit incorporating a Schmitt trigger as an action potential generating component. The Schmitt trigger is composed of four MOSFETs, and it presents hysteresis by controlling the threshold of one of the four MOSFET using back-gate effect. The presented circuit effectively handles input overflow by modulating output pulse duration, thus maintaining Rectified-linear-unit (ReLU) equivalence of I&F spiking neuron. The effect of overflow handling by output pulse modulation was further investigated by comparing the performance of single-layer spiking neural network (SNN) implemented using proposed circuit and conventional circuit. The ex-situ (offline) triained SNN implemented using the proposed circuit showed 1.8%p accuracy improvement in classifying 1000 MNIST handwritten digits compared to one implemented using conventional I&F neuron circuit due to elimination of quantization error.

Demonstration of GaN Integrated Half-Bridge With On-Chip Drivers on 200-mm Engineered Substrates

Co-integration of the key power stage, namely gate drivers and half-bridge in a single-die solution, is a tremendous and inevitable challenge to realizing GaN power integrated circuits (GaN power ICs). In this letter, a monolithically integrated GaN half-bridge including the drivers were successfully fabricated on 200-mm engineered substrates of Qromis substrate technology (QST®). Deep trench isolation together with the buried oxide of the GaN-on-QST® isolates the high side, low side, and the drivers. While on GaN-on-Si, the back-gating effect more and more impedes the integration of a half-bridge’s low side and high side as the voltage increases. This effect is fully eliminated using the proposed effective isolation strategy. In this letter, we will present a single-die GaN power IC exhibiting 200-V swift switching capability. Finally, based on this GaN power IC, a 48V-to-1V single-stage buck converter was successfully demonstrated.

Probing the Field-Effect Transistor with Monolayer MoS2 Prepared by APCVD.

The two-dimensional materials can be used as the channel material of transistor, which can further decrease the size of transistor. In this paper, the molybdenum disulfide (MoS2) is grown on the SiO2/Si substrate by atmospheric pressure chemical vapor deposition (APCVD), and the MoS2 is systematically characterized by the high-resolution optical microscopy, Raman spectroscopy, photoluminescence spectroscopy, and the field emission scanning electron microscopy, which can confirm that the MoS2 is a monolayer. Then, the monolayer MoS2 is selected as the channel material to complete the fabrication process of the back-gate field effect transistor (FET). Finally, the electrical characteristics of the monolayer MoS2-based FET are tested to obtain the electrical performance. The switching ratio is 103, the field effect mobility is about 0.86 cm2/Vs, the saturation current is 2.75 × 10−7 A/μm, and the lowest gate leakage current is 10−12 A. Besides, the monolayer MoS2 can form the ohmic contact with the Ti/Au metal electrode. Therefore, the electrical performances of monolayer MoS2-based FET are relatively poor, which requires the further optimization of the monolayer MoS2 growth process. Meanwhile, it can provide the guidance for the application of monolayer MoS2-based FETs in the future low-power optoelectronic integrated circuits.

Effect of high-K dielectric on differential conductance and transconductance of ID-DG MOSFET following Ortiz-Conde model

Differential conductance and transconductance of double-gate MOSFET are analytically computed in presence of high-K dielectric following Ortiz-Conde model. Poisson’s equation and carrier continuity equation are simultaneously solved incorporating the effect of back-gate, and independent-gate model is considered for electrical characterization. Percentage change of conductance and transconductance are calculated, and results are compared with published literature. Effect of high-K dielectric is analyzed with that obtained for conventional SiO2 materials where comparison is taking place with identical bias and structural parameters. Saturation of transconductance is obtained for high-K dielectrics for higher VGS and lower VDS, indicating the subthreshold condition. Pinch-off condition is also evaluated from the plot of differential conductance. Results are extremely useful for utilizing the device for analog and digital circuits with nano-device.

Atomic layer deposition growth of SnS2 films on diluted buffered oxide etchant solution-treated substrate

In this report, two types of substrates were prepared for deposition of few-layer tin disulfide (SnS2) via atomic layer deposition (ALD). The first substrate was prepared using a conventional cleaning method, while the second substrate was rinsed with buffered oxide etcher (BOE) solution after conventional cleaning. Changes in the substrate were confirmed by X-ray photoelectron spectroscopy, contact angle measurements, and electron spin resonance. Characteristics of the SnS2 thin films were determined by X-ray diffraction, Raman analysis, Fourier transform-infrared spectroscopy, atomic force microscopy, and X-ray photoelectron spectroscopy. To investigate growth rate, thickness was measured as a function of ALD cycle number by atomic force microscopy, and 2D layered structure was confirmed by transmission electron microscopy. Findings confirmed that surface treatment using BOE solution was related to an increased growth rate during the initial ALD process. Finally, back-gate field effect transistors based on ALD-grown SnS2 film prepared on substrate that received diluted-BOE surface treatment showed marginal improvement in current on/off ratio from 2.9 × 105 to 6.5 × 105 and mobility from 0.22 cm2/Vs to 0.31 cm2/Vs compared to ALD-grown SnS2 film prepared on bare substrate.

Analysis of back-gate effect on threshold voltage of p-channel GaN MOSFETs on polarization-junction substrates

GaN-based p-channel devices using a two-dimensional hole gas are of interest for the realization of GaN CMOS circuits, and threshold voltage control using a back-gate is useful for the circuit design of these devices. In this paper, the back-gate effect on p-channel GaN MOSFETs on polarization-junction substrates is studied. The results show that the obtained dependence of the threshold voltage on the back-gate voltage can be derived by a model equation considering the back surface channel. Also, by comparing the measured characteristics with the simulation result under ideal conditions, it is found that the amount of interfacial charges can be quantitatively evaluated for the fabricated device.

An Analytical Drain Current Model of Gate-On-Source/Channel SOI-TFET

This paper presents an analytical drain current model of Gate-on-Source/Channel SOI-TFET. While deriving the drain current, at first surface potential is derived considering the effect of back gate and considering the effect of bandgap narrowing, energy bands are derived from this surface potential. Finally, the drain current model of Gate-on-Source/Channel SOI-TFET is developed using maximum generation rate of the device. Considering the effect of local minimum present in the energy band diagram of Gate-on-Source/Channel SOI-TFET, maximum generation rate is calculated using a different approach by considering the difference of surface potential between the source region with no gate overlap and the position of local minimum. The proposed model is investigated for front gate voltage, back gate voltage, drain voltage variation. Scalability of the proposed model is analyzed by changing the front gate oxide thickness and body thickness. The model results are compared with the TCAD simulated data to validate the model.

Electrical Transport Properties of Self-Organized ZrO2 Nanotube

Self-organized ZrO2 nanotubes are prepared via the conventional anodization method. Back-gate field effect transistors are fabricated for the first time to study the electrical transport properties of single ZrO2 nanotube The drain current increases with the applied negative gate voltage, which is suggesting the ZrO2 nanotube works under hole accumulation mode. The room temperature hole mobility of 0.03 cm2 V-1s−1 and average hole concentration of 2.8 × 1018 cm−3 are obtained at low drain bias. Temperature dependent I-V characteristics show that the hole concentration and hole mobility have an opposite changing trend with the temperature. The current of the device is controlled by the offset effect between the hole concentration and hole mobility.

Fully Depleted SOI Pixel Detector With Multijunction Structure in p-Type Substrate

A fully depleted silicon-on-insulator (SOI) pixel detector with multijunction structure in p-type substrate is proposed to reduce the diode capacitance and improve the effective shielding between the SOI circuits and sensor. A buried p-well (BPW) and a buried n-well (BNW) are applied to their respective bias voltages to shield SOI circuits from the sensor in the substrate. BPW is biased to counteract the back-gate effect. A deeply BPW is employed to form a potential barrier to electrons in BNW, stopping the front-to-back leakage current. Lateral electric field is also formed to accelerate holes to the p+ charge collector. The simulation results demonstrate that the pixel can achieve its objectives under a full depletion condition. The capacitance of the charge collector can be reduced, which depends primarily on the charge-collector/BNW junction.

Graphene/In2S3 van der Waals Heterostructure for Ultrasensitive Photodetection

As an emerging 2D nonlayered material, natural defective β-In2S3 nanosheets have drawn attention because of their unique defective structure and broad optical detection range. Stacking n-type In2S3 with other p-type 2D materials can produce an atomically sharp interface with van der Waals interaction, which may lead to high performance in (opto)electronics. In this study, we fabricated a van der Waals heterostructure composed of In2S3 and graphene via the dry transfer method. Scanning Kelvin probe force microscopy revealed a significant potential difference at the interface of the heterostructure, thereby endowing it with good diode characteristics. The back-gate field effect transistor based on the graphene/In2S3 heterostructure exhibited excellent gate-tunable current-rectifying characteristic with n-type semiconductor behavior. A photodetector based on the graphene/In2S3 heterostructure showed excellent response to visible light. Particularly, an ultrahigh responsivity of 795 A/W and an external quantu...

Electrical Properties of Exfoliated Multilayer Germanium Selenide (GeSe) Nanoflake Field-Effect Transistors

We report on the electrical properties of natural p-type GeSe nanoflakes, which were mechanically exfoliated from GeSe single crystals by the polydimethylsiloxane (PDMS) stamp method, using a back-gate field effect transistor (FET) measured in a vacuum probe station at room temperature. In this study, we used two contact metals, including Au and Cr metals, as the Ohmic contacts to the GeSe nanoflake FETs, resulting in an Ohmic behavior with the Au contacts, with a total resistance of 5.5 × 106 Ω. We also found that the 40-nm-thick GeSe nanoflake FET exhibits clear p-type semiconductor behavior with a field-effect mobility of ∼1.0 × 10–3 cm2/(V · s) and a current on/off ratio of ∼104 at room temperature.

Integrate‐and‐fire spiking neuron circuit exhibiting spike‐triggered adaptation through input current modulation with back gate effect

The authors present a spike-triggered adaptive neuron circuit with input current modulation. Unlike adaptive neuron circuits where adaptation is realised by leakage modulation, the circuit presented in this Letter modulates the input current to membrane capacitor. Therefore, it is possible to reduce extra power consumption originating from increased leakage. Threshold voltage modulation of silicon on insulator (SOI) MOSFET by back gate effect is used to change the amount of injected current for the same input voltage. Through this method, the circuit in this work consumed 25.9% less power than the one modulating leakage.

Suppression of the Backgating Effect of Enhancement-Mode p-GaN HEMTs on 200-mm GaN-on-SOI for Monolithic Integration

The backgating effect on trench-isolated enhancement-mode p-GaN devices fabricated on 200-mm GaN-on-SOI was investigated. We show that to minimize the backgating effect in the monolithically integrated half-bridge, the sources of both the low side and high side need to be connected to their respective fully isolated Si(111) device layers to keep the substrates and the sources at equipotential.

Impact of Substrate Resistivity on the Vertical Leakage, Breakdown, and Trapping in GaN-on-Si E-Mode HEMTs

This paper presents an extensive investigation of the impact of the resistivity of the silicon substrate on the vertical leakage and charge trapping in 200 V GaN-on-Si enhancement-mode high-electron mobility transistors. Three wafers having different substrate resistivities were submitted to combined DC characterization, step-stress experiments, and electroluminescence (EL) analysis. The results described within this paper demonstrate that: 1) the use of a highly resistive silicon substrate can increase the vertical breakdown voltage of the transistors, due to the fact that the voltage drop on the GaN buffer is mitigated by the partial depletion of the substrate (this latter causes a plateau region in the drain to substrate I–V characteristic) and 2) highly resistive substrate results in stronger trapping effects, due to the capacitance of the depleted substrate and the resulting backgating effects. The results described within this paper indicate that the choice of the resistivity of the substrate is the result of a tradeoff between high breakdown voltage (that could be in principle achieved through a highly resistive substrate) and the minimization of trapping processes (which can be hardly obtained with a resistive substrate).

MAPS sensor for radiation imaging designed in 180 nm SOI CMOS technology

In this work, we present a prototype of the Monolithic Active Pixel Sensor (MAPS) called X-CHIP-02 designed in 180 nm SOI CMOS technology. The selected technology has attractive features for fabrication of X-ray imaging sensors: 100 Ω⋅ cm handle wafer resistivity, thick epitaxial layer to suppress back-gate effect, support of high voltage devices and deep trench isolation. X-CHIP-02 has two pixel matrices with the pixel pitch of 50 μm and 100 μm with integrated 8-bit photon counting circuitry. Fine pitch SOI monolithic pixels imply small capacitance and thus small electronic noise of ≈50 e−. Design of the sensor chip and basic radiation imaging capabilities are described in this paper.

Accurate Modeling of GaN HEMT RF Behavior Using an Effective Trapping Potential

This paper investigates the back-gating effects due to traps, and presents a new nonlinear trap modeling approach suitable for gallium nitride (GaN) high electron mobility transistors (HEMTs). It is shown that the traps have nonidentical influence on the channel compared with the gate. The potential due to trapped electrons in the buffer and the gate–source voltage need to be differentiated to model their respective influence on conductivity of the 2-D electron gas. Hence, the back-gating potential due to traps cannot be included in the transistor model by directly offsetting the gate–source voltage. A new modulation factor is therefore introduced to create an effective back-gating potential, and thereby improve the modeling of trapping effects. The proposed nonlinear trap model is shown to accurately predict the trapping behavior for a large voltage operating region. A detailed procedure is presented to derive the model parameters from basic device measurements. The model is experimentally validated and shown to accurately predict dc-, pulsed-IV, and large-signal waveform performance for a commercial GaN HEMT.