Back-gate Effect Research Articles

Gate Coupling and Charge Distribution in Nanowire Field Effect Transistors

We have modeled the field and space charge distributions in back-gate and top-gate nanowire field effect transistors by solving the three-dimensional Poisson's equation numerically. It is found that the geometry of the gate oxide, the semiconductivity of the nanowire, and the finite length of the device profoundly affect both the total amount and the spatial distribution of induced charges in the nanowire, in stark contrast to the commonly accepted picture where metallic dielectric properties and infinite length are assumed for the nanowire and the specific geometry of the gate oxide is neglected. We provide a comprehensive set of numerical correction factors to the analytical capacitance formulas, as well as to numerical calculations that neglect the semiconductivity and finite length of the nanowire, that are frequently used for quantifying carrier transport in nanowire field effect transistors.

Characterization of double gate TFTs fabricated in advanced SLS ELA polycrystalline silicon films

Double gate thin film transistors (TFTs) were fabricated in advanced excimer-laser annealed (ELA) polycrystalline silicon films, obtained by sequential lateral solidification (SLS), and their characteristics were investigated. The observed back gate effect on the I DS–V GS on–off curves indicated fully depleted active layers. The dependence of the device parameters for front gate operation on the back gate bias reflected the conduction behavior, with varying back channel contribution. While the double gate structure needs to be optimized for highest performance, the use of the back gate was determined both to result in effective threshold control, allowing for design flexibility, and also to make possible a reduced avalanche effect for similar drain current levels.

Analysis of the back-gate effect on the breakdown behavior of lateral high-voltage SOI transistors

A novel back-gate reduced bulk field concept which makes a breakthrough in improving the vertical breakdown voltage of high voltage SOI transistors is proposed. The mechanism of the improved breakdown characteristics is that the electric field distributions of the active region are modulated by the interface charges induced by the back-gate voltage. The bulk electric field at the drain side is reduced, the bulk electric field at the source side is increased, and the breakdown voltage of the high voltage SOI device is improved. The impact of the back-gate bias on thick film SOI LDMOS (over 600 V) is discussed via two-dimensional simulations. When the back-gate bias is 330V, the breakdown voltage of the three-zone SOI double RESURF LDMOS is 1020V, which is 47.83% greater than that of a conventional LDMOS. The novel concept presents a new method for realizing over 600 V high voltage power device and high voltage integrated circuit.

A new analytical model for photo-dependent capacitances of GaAs MESFET’s with emphasis on the substrate related effects

A new analytical model for optical and bias dependent nonlinear capacitances of GaAs MESFET which is valid for both linear and saturation regions has been proposed in this paper. The novelty lies in modeling of internal and external photovoltaic effects that includes deep level traps in the substrate and surface recombination at metal–semiconductor interface of the gate. The effect of high field domain formation at the drain end in the saturation region has also been included to improve the accuracy of the present model. The model presents backgating effects on gate–source and gate–drain capacitances of GaAs MESFET for the first time in literature. Finally, the proposed model has been compared to the reported results to show the validity. The proposed model may be very useful for the designing of photonic MMIC’s and optical receivers using GaAs MESFET’s.

Analysis of the Back-Gate Effect on the on-State Breakdown Voltage of Smartpower SOI Devices

This paper discusses the impact of the back-gate bias on the on-state drain breakdown voltage of high-voltage silicon-on-insulator (SOI) MOSFETs. This is mandatory in order to understand the physical mechanisms behind the limitations of the safe operation area (SOA) of SOI power devices. The back-gate electrode of the SOI material will add an additional dimension to the SOA, thereby causing further reliability constraints on the circuit design. For small and negative back-gate bias, the SOA is limited by the on-state breakdown whereas the off-state breakdown sets the limit for positive back-gate bias. For the first time, an analytical model of the breakdown voltage covering the reasonable back-gate voltage range is presented providing a first step toward a closed form circuit simulation of this effect. It is shown that the back-gate potential impacts on the breakdown behavior by modulating the carrier distribution in the drift region, the base transport factor of the parasitic bipolar transistor, and the drift region resistance. Moreover, it is shown that avalanche multiplication is the limiting breakdown mechanism for lateral SOI power devices

Temperature and Illumination Dependence of AlGaN/GaN HFET Threshold Voltage

This investigation of the temperature and illumination effects on the AlGaN/GaN HFET threshold voltage shows that it shifts about -1 V under incandescent lamp or blue LED illumination, while almost no shift takes place under red LED illumination. The temperature coefficient for the threshold voltage shift is +3.44mV/deg under the illuminations and +0.28 mV/deg in darkness. The threshold voltage variation can be attributed to a virtual back-gate effect caused by light-generated buffer layer potential variations. The expressions for the potential variation are derived using Shockley-Read-Hall (SRH) statistics and the Maxwell-Boltzmann distribution for the carriers and deep traps in the buffer layer. The expressions indicate that large photoresponses will occur when the electron concentration in the buffer layer is extremely small, that is, highly resistive. In semi-insulating substrates, the substrate potential varies so as to keep the trap occupation function constant. The sign and the magnitude of the threshold voltage variation are explained by the shift of the pinning energy calculated from the Fermi-Dirac distribution function.

Time Resolved Photoconduction Studies of Uniformly Doped and p-n Junction Si Nanowires

ABSTRACTThe time resolved and DC photoconduction characteristics of Si nanowire devices are described. Si nanowires with diameters ranging from 20-100 nm were grown using the vapor-liquid-solid (VLS) growth mechanism under standard conditions and devices were fabricated in a back-gate field effect transistor (FET) configuration using simple photolithography. It is shown that under certain biasing conditions, illumination with light from light emitting diodes with wavelengths ranging from 480 nm to 625 nm causes changes in current as high as 4%. On the other hand, illumination by a broadband incandescent source causes a ∼4.1% percent change in current. Photoconductive decay curves show bi- and tri-exponential behavior, indicative of multiple potential recombination mechanisms occurring within the Si nanowire devices. p-n doped Si nanowires show similar behavior. Studies under various drain and gate voltages provides insight into the proposed mechanism. It is argued that the Shottky barrier plays a strong role in the observed photoconduction process in these wires, as do transitions involving surface and deep level trap states.

Back-Gate Effect on Coulomb Blockade in Silicon-on-Insulator Trench Wires

A back-gate (BG) effect on a Coulomb blockade in a double-gate silicon-on-insulator (SOI) nanowire is investigated. The nanowire, which is situated at the bottom of a trench and connected to thicker source/drain regions, has a naturally formed barrier at both ends and works as a single-electron transistor at low temperatures. We found that a negative BG voltage increases the charging energy of the Coulomb-blockade island in the nanowire as well as the tunnel resistance of the barriers. This indicates the possibility that the BG voltage shifts the electron wave functions in the source/drain area away from the Coulomb-blockade island and decreases the capacitance of the small junctions located at both ends of the island.

Analysis and Optimization of the Back-Gate Effect on Lateral High-Voltage SOI Devices

This paper discusses for the first time the impact of the back-gate bias on lateral DMOS (LDMOS) transistors on silicon-on-insulator (SOI) substrates. An analytical model that takes the back-gate bias and the device parameters into account is presented and verified with a 0.8-/spl mu/m, 80-V SOI smart power technology. It will be explained that the effect of the back-gate bias on the LDPMOS devices is directly opposed to the LDnMOS transistors. The p-channel and the n-channel devices require different design strategies for the optimal buried oxide thickness due to the effect of the back-gate. A new device structure, namely body buried oxide step structure (BBOSS) that locally weakens the effect of the back-gate is presented. The proposed new structure allows a separated optimization of the buried oxide thickness without affecting the on-resistance.

Back-Gate Effect to Generate Derivative of Neuron Activation Function

A simple neuron circuit is presented which can generate the sigmoid neuron activiation function (NAF) and its derivative (DNAF) by introducing asymmetric body biasing in the cross-coupled differential pair. The mode of operation is controlled externally. This results in the efficient utilization of the hardware by realizing NAF and DNAF using the same building blocks. The circuit is prototyped and characterized as a proof of concept on 1.5 μm AMI technology.

Fabrication of carbon nanotube field effect transistors by AC dielectrophoresis method

Single wall carbon nanotubes (SWNTs) suspended in isopropyl alcohol have been placed between two electrodes by AC dielectrophoresis method. The number of SWNTs bridging the two electrodes is controlled by SWNT concentration of the suspension and deposition time. Through selectively burning off the metallic SWNTs by current induced oxidation, the back-gate carbon nanotube field effect transistors (CNTFETs) with a channel current on–off ratio of up to 7 × 10 5 have been successfully fabricated. The success rate of the CNTFETs in 20 samples is 60%. These results suggest that AC dielectrophoresis placement method is an efficient technique to fabricate CNTFETs with some flexibilities of controlling CNT reconnection, length and orientation.

Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs

This paper investigates the influence of the silicon substrate on the ac characteristics of silicon-on-insulator (SOI) MOSFETs. It is shown for the first time that the presence of the substrate underneath the buried oxide results in two transitions (i.e., zero-pole doublets) in the frequency response of the output conductance. It is demonstrated that the appearance of these transitions, the position and amplitude of which strongly depend on the substrate doping, is caused by the variation of the potential at substrate-buried oxide interface, which we call the Floating Effective Back-Gate (FEBG) effect. A first-order small-signal equivalent circuit is proposed to support our observations.

High-purity semi-insulating 4H-SiC for microwave device applications

High-purity, semi-insulating (HPSI) 4H-SiC crystals with diameters up to 75 mm have been grown by the seeded sublimation technique without the intentional introduction of elemental deep-level dopants, such as vanadium. Wafers cut from these crystals exhibit homogeneous activation energies near mid gap and thermally stable semi-insulating (SI) behavior (>109 ohm-cm) throughout device processing. Secondary ion mass spectroscopy, deep-level transient spectroscopy, optical admittance spectroscopy, and electron paramagnetic resonance data suggest that the SI behavior originates from several deep levels associated with intrinsic point defects. Micropipe densities in HPSI substrates have been demonstrated to be as low as 10 cm−2 in 2-in. substrates, and the room-temperature thermal conductivity of this material is near the theoretical maximum of 5 W/cm·K for 4H-SiC. Devices fabricated on these HPSI wafers do not exhibit any substrate related back-gating effects and have power densities as high as 5.2 W/mm with 63% power added efficiency.

Investigation of AlGaN/GaN HEMTs on Si Substrate Using Backgating

The influence of a substrate voltage on the dc characteristics of an AlGaN/GaN HEMT on silicon (111) substrate is investigated. This effect, known as backgating, is used to study traps that are located between substrate and 2DEG channel. The transient of the drain current after applying a negative substrate voltage is evaluated for measurements with and without illumination. Several trap contributions are resolved by measurements at different photon energies. A photocurrent is observed up to 600 nm wavelength. Up to this wavelength the backgating effect can be compensated and the drain current restored by a short light pulse. The experiments are performed on completed HEMTs, allowing investigation of the influence of device fabrication technology.

Back gate effects on threshold voltage sensitivity to SOI thickness in fully-depleted SOI MOSFETs

The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide thickness and back gate voltage are varied. When the back gate oxide is thinner than the critical thickness dependent on the back gate voltage, the threshold voltage has a minimum in cases where the SOI film thickness is decreased, because of capacitive coupling between the SOI layer and the back gate. This fact suggests that threshold voltage fluctuations due to SOI thickness variations are reduced by controlling the back gate voltage and thinning the back gate oxide.

Back-gate and series resistance effects in LDMOSFETs on SOI

Detailed experimental results are used to develop a new model for the linear region of operation of lateral DMOSFETs (LDMOSFETs) on silicon-on-insulator (SOI) that includes the influence of the buried oxide and back-gate. Back-gate biasing results in double-channel conduction and bias-dependent series resistance. Pertinent techniques for parameter extraction are presented and contrasted to those currently used in low-voltage SOI MOSFETs. The typical feature of LDMOSFETs is the significant change in series resistance as the back-gate is driven from accumulation to inversion. The model allows a clear identification of the architectural and technological parameters of the device.

A 1-Kbit EEPROM in SIMOX technology for high-temperature applications up to 250/spl deg/C

A 1-Kbit high-temperature EEPROM memory module has been developed in a 1.6-/spl mu/m thin-film SIMOX technology. The memory array is based on single-poly EEPROM cells, which are erased and programmed by Fowler-Nordheim tunneling. Operation at elevated temperatures is achieved by a special array design, suitable for elimination of cell-disturb problems caused by temperature-induced leakage currents of the select transistors. High-voltage switching is done without PMOS transistors in order to avoid leakage currents due to the backgate effect. The memory module is designed for 5-V only operation and offers an access time of 260 ns at an operating temperature of 250/spl deg/C. At 250/spl deg/C, data retention of 3000 h and an endurance of 10000 erase/program cycles has been achieved. The area of the 1-Kbit memory module is 0.89/spl times/2.71 mm/sup 2/.

Semiconductor thickness and back-gate voltage effects on the gate tunnel current in the MOS/SOI system with an ultrathin oxide

The effects of the semiconductor layer thickness and the back-gate voltage on the current-voltage (I-V) characteristics of the MOS/SOI tunnel diode with an aluminum gate and n-type semiconductor layers are theoretically investigated. If the semiconductor thickness is reduced or the back-gate voltage is more negative, the total thermal generation current decreases and the gate-oxide thickness critical for transition from the quasiequilibrium strong inversion state to the nonequilibrium state increases. If the MOS/SOI tunnel diode is in the transition range between the nonequilibrium and quasiequilibrium states, a positive increase of the back-gate voltage V/sub BG/ results in a strong increase of the majority carrier tunnel current. This back-gate effect may be exploited in more functional devices based on the MOS/SOI tunnel diode.

Back Gate Effects in N-Channel Monocrystalline Silicon Devices-on-Glass and their Suppression by Boron Ion Implantation

ABSTRACTInitial N-channel self aligned polycrystalline silicon gate transistors fabricated on 1.5μm -2μm single crystal Silicon-O-Glass(SOG) layers exhibited poor transfer characteristics. Measured threshold voltages and On/Off current ratios were in the order of -8V and 10 respectively. This is due to the presence of fixed charge at the bond interface introducing back gate effects which degrade and distort device performance. These back gate effects were suppressed by implantation of boron into the silicon substrate prior to oxidation and bonding, with energy 40keV and dose 7.4×1012cm−2. This resulted in an improvement in device performance with a threshold voltage of-0.54V. On/Off current ratio increased to 1840 and field effect mobility increased from 274cm2/Vs to 357cm2 Vs

A three-parameters-only MOSFET subthreshold current CAD model considering back-gate bias and process variation

In this paper we introduce a new subthreshold conduction CAD model for simulation of VLSI subthreshold CMOS analog circuits and systems. This model explicitly formulates the back-gate bias effect and preserves the original advantages of the existing four-parameter model while reducing the fitting parameter number down to three. A transparent relationship between the fitting parameters and the process parameters has been derived, and its correlation with a recently widely used CAD model as well as with a well-known two-parameter model has been established. Our extensive measurement work on n-channel MOSFET's has highlighted the potential of the model in handling the variations in the subthreshold I-V characteristics at different back-gate biases arising from process variations. The mismatch analysis has further been successfully performed with emphasis on the reverse back-gate bias effect. In summary, the proposed model can serve as a promising alternative in the area of VLSI subthreshold CMOS analog circuit simulation.